Engineer Design
Resume:
John Beck
**** ****** **** *****, ****** TX *****
******@*****.***
Experience:
Highly Creative Problem Solver
Team and Project Leadership
IC Design
CMOS, NMOS and GAAS
Architecture and Specification of entire chips, sub-blocks, and
chip sets
Logic And Circuit Design including Power/Speed/Area Control
Timing Analysis and Simulation, both Logic and Circuit Levels
Full Custom and Standard Cell - 55 nm and above
Cell Library Design and Development
Flow, and Tools set development and validation
Clock and Power distribution, planning, and specification
Noise Analysis and Remediation
High Speed Digital I/O
Patents:
linear jitter attenuation; load/store control; high speed adders;
static and dynamic circuitry, noise reduction and signal integrity
Skills:
Tools: Synopsis, Cadence, and Mentor tools, Verilog and VHDL, SPICE,
Eldo, Calibre, PATHMILL, TIMEMILL, ECAD, LVS, DRC. Several "in-house"
tools (Intel/IBM). Quickly adapt to new tools and releases.
Operating Systems and Computer Languages: UNIX/LINUX, Windows, DOS.
Scripting Languages: Perl, AWK, Tcl/tk.
Interests:
Technical Management; IC or Board Design, Application Support;
Robotics, Neural Networking, Multiprocessing, Artificial
Intelligence, Signal and Image Processing, Computers and Computer
Networks, Technical Support
Project Summary:
Cypress Semiconductor - Contractor (Design Engineer), Seattle, WA 12/07-
04/08
Clock delay and skew simulations.
Spice-based timing simulations for major block of UDB device.
Critical path modeling and analysis, including interconnect loading. All
simulations tracked extracted layout data.
Functional and timing simulations. Improved timing and functionality.
Cswitch - Contractor (Design Engineer), San Jose, CA 9/06-10/06
Clock delay and skew simulations.
Simulated various options to reduce clock skew across process, voltage, and
temperature.
Wrote scripts to simplify submission of spice jobs across process, voltage
and temperature.
Wrote scripts to assist in identifying layout cell to Spice netlist names
across a hierarchical design, for black-box Calibre extractions.
Ran Caliber extractions for clock distribution blocks, and ran
characterizations on those blocks for timing analysis.
Chip was an ethernet/fiber FPGA type programmable switch fabric.
Intel - Contractor (Design Engineer), Chandler, AZ 7/05-7/06
Timing analysis for multiple blocks of an embedded microprocessor.
Cell library validation for speed, voltage swing, set up and hold margins,
scan functionality.
Logic verification of library cell function.
startup - Design Engineer, Austin, TX 4/02-7/05
Created architecture, wrote specifications, supervised and wrote Verilog
RTL simulation logic and circuit design of high speed parallel
microprocessor (500MHz to 1GHz). Supervised and wrote program code and
scripts for demonstrations and end user usage. Supervised C simulator
coding and coding of graphical programming tool.
Specified Ptolemy-based programming approach for pre-coded end user system
solutions.
SPEC - Design Manager, Austin, TX 5/99-4/02
Brought in own design of high speed parallel processor, including
architecture, specifications, all performance metrics.
Developed custom, transistor level design including register files, ALU and
control logic, including critical path analysis.
Wrote Verilog tests for verification and simulation.
Led team in development of algorithms and software.
Designed high speed GaAs standard cells and I/O.
Wrote SBIRs, and contract proposals.
Performed LVS and DRCs.
Performed Technical and Layout Supervision.
Guided computer, software, and tools purchase and installation.
Ross Technologies - Senior Engineer, Austin TX 9/97-7/98
Team Lead.
Oversaw all phases of development of IEEE compliant Floating Point Unit.
Designed logic and circuitry for floating point adder for 500 MHz Viper
chip.
IBM - Staff Engineer, Austin, TX 5/95-9/97
Transistor level design of various 64 bit modules for Power PC
Microprocessors.
Modified Load/Store Unit to substantially reduce total gate delay, allowing
1 Ghz operation, simultaneously reduced total control logic by 90 per cent,
while achieving two stages of data path logic reduction.
Static and dynamic transistor design; met all required safety margins, and
exceeded the target for 1 GHz operation.
Multiple patent applications filed, including Load/Store unit, 64 bit fixed
point adders, digital line noise coupling reduction, several dynamic logic
circuit techniques, and a multi-processor bus interface.
Contributed presentation of dynamic design techniques for design staff.
More experience available upon request.
Education:
MSEE and BSEE, Texas A&M University.
Thesis: A Dual Adaptive Hybrid Encoder - a dual adaptive, hybrid DCT-
time domain based, bit compression scheme for digitized images.
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