Engineer Software

Prabhjot Billing

*** * *** ** ***# *

****************@*****.***

San Jose, CA - 95112

Phone: 408-***-****

OBJECTIVE

Seeking a Full time /Internship position in medical devices Industry.

EDUCATION

Master of Science in Electrical Engineering (GPA: 3.6/ 4)

San Jose State University, San Jose, CA

Dec'10

Bachelor of Technology in Electronics and Communication (Percentage: 71

/ 100)

Jay Pee University of Information Technology (JUIT), India

May '07

RELEVANT COURSES

. Analog Integrated Circuits

. Internetworking

. High Speed CMOS Circuits

. Semiconductor Devices

. ASIC CMOS Design

. Linear System Theory

. Digital System Design and Synthesis

. Microprocessors and Microcontrollers

EXPERIENCE

Verification Engineer : Syneron Inc (previously Primaeva Medical Inc.,

Pleasanton Jan 2010-Present

. Working as an verification engineer intern to test and

troubleshoot a Radio Frequency (RF) device

designed to treat skin wrinkles.

. Responsibilities include writing protocols for hardware and

software verification, performing

Chip level/software/system testing and writing reports on

findings and troubleshooting the defects..

. Working closely in teams with R&D department to test the RF device.

Instructional Student Assistant: San Jose State University

Aug 2009-Present

. Working as ISA in Mathematics Department.

. Graded and helped the students with homework Assignments for undergrad

Courses

(Differential Equations, Applied combinatorics, Differtial

Calculus).

Software Engineer: Keane India Ltd, Gurgaon (India)

Aug 2007 - July 2008

. Project for Philip Morris USA (PMUSA)

. Experience of 11 months in IBM Mainframe technologies

. Work process includes Requirement Capture, Solution Design,

Coding, Testing, Implementation And Support

. Primary responsibilities include Development and Maintenance of

client applications. This Includes Estimation and preparation of

Statement of Work (SOW), Requirement Traceability Matrix (RTM)

and Unit Test Plan (UTP). This is followed by coding, testing,

package Implementation and providing support during User

Acceptance Testing (UAT)

. Worked efficiently individually and in teams of various sizes to

complete assigned projects.

Internship: Semi-Conductors Complex Limited, Mohali,INDIA

June-July 2005

. Learned Verilog language for digital design and Synthesis

tools.

. Designing and Implementation of Logic Devices using Xilinx

tools.

. Completed a project 8 bit parallel Fast Multiplier using VERILOG

ACADEMIC PROJECTS

64 Bit ALU(Arithmetic Logic Unit) design

Fall 2009

. Designed schematic and layout of 64 bit ALU running at 4 GHz using

dynamo logic family and conducted Pre and Post Layout Simulations

. Performed DRC and LVS clean layout and carried out RC Parasitic

Extraction

Data Unconfuser

Spring 2009

. Developed a Data Processing Engine in Verilog for low level data

encryption.

. CRC shift registers are used to decrypt the data based on the key

received from the transmitter.

. A FIFO is used at the input and output to synchronize the data speed

between the transmitter and unconfuser and to prevent

data loss.

. Successfully synthesized the design using Toshiba Library for

operation at 180Mhz.

Sequential Shift-Add Multiplication Circuit

Spring 2009

. Completed RTL Coding for Sequential Shift Add Multiplication Circuit

in Verilog.

. Different Addition algorithms like Carry Look Ahead are used to

increase the Multiplication speed.

. The design is synthesized using Toshiba libraries using VCS tool.

Single Ended two stage Operational-Amplifier

Fall 2009

. Designed and Optimized a single ended two stage OP-AMP circuit for

desired specifications using 90nm CMOS library.

. The Schematic and Layout of OP-AMP was designed using Cadence Virtuoso

tool.

. Spectre simulator was used to test the performance of the circuit

through different testbenches

SKILLS

( Languages: Verilog HDL, C, C++, Assembly language (Intel 8085, 8086),

VHDL, COBOL, JCL, Endevour, easytriev

(General: SPICE analysis & simulation, DRC (Design Rule Check) & LVS

(Layout vs. Schematic),

Pre & post layout simulation, RTL simulation and

synthesis

( Tools: CADENCE Virtuoso, Synopsis VCS, Matlab, Sentaurus Work

Bench (SWB), XILINX ISE, NC Verilog,

Wireshark,OPNET

( Database: DB2, SQL Server

. Operating Systems: UNIX, Windows XP/Vista/Me

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