Electrical Engineer Project

Kenneth B. Coulthart

*** ****** *******

Hackettstown, NJ 07840

*******@*****.***

H: 908-***-****

C: 908-***-****

Classification: Principal Engineer- Electrical

SKILLS IN:

DIGITAL DESIGN CHIP DESIGN (ASIC or FPGA) PROGRAMMING

USING LANGUAGES:

VHDL ( SYNOPSYS) QBASIC C, C++

YACC & LEX FORTRAN LABVIEW / LABWINDOWS

ON SYSTEMS:

UNIX WINDOWS XP

MICROPROCESSORS DSP PROCESSORS

GPIB (National's GPIB & acquisition)

SUMMARY:

Accomplished Electrical Engineer in hardware integration and testing. An

experienced problem solver focused on driving critical issues to

resolution.

* Hold a Top Secret / SCI with polygraph security clearance since 1990.

* Principal Engineer with thirty-four years of experience.

WORK EXPERIENCE:

AREA Z7286300 MILITARY General Dynamics

(Florham Park, N J) Advanced Technology Systems

2006 to Present:

Responsible for designing, testing & debugging system cards within the

project bay. Cards include: Control, UPS, Power Supplies, communication,

ESD protection and inspections.

2003 to 2005: Designed three optically based prototype cards (Optical

Switch, Command & Control, Optical Filter) for an optical control system.

Responsible for parts selection, board layout, inspection, and all test uP

software written, debugged (two different CPUs & FPGAs were written to

each card with different control software), peer inspections.

2000 to 2002: Design responsibility for communication cards: Serial, RS-

232, RS-422, RS-485, IRIG control, "S" Panel, and "T" Panel cards;

Includes card designing, CPLD programming (VHDL), & card testing. Created

LabWindows (C language) debugging GUI programs ("KDIO") for field testing.

Wrote test specifications for these cards and modules.

1999 to 2000: SEA PLOW project: Responsible for plow interface data

communications: software & hardware of navigation, GPS, sonic ranging

devices and plow sensor data, data processing (conversion into engineering

units, database storage and post processing). Designing LabWindows GUI

interfaces for various simulators to test project hardware.

AREA 46---MILITARY (Lucent Advanced Technology Systems)

1997-1998: Wrote ETCDM controller software, GUI (user interfaces) and data

post processors with graphics plotters. Analog & digital data acquisition

using Visual C++ 4.0.

1996: Wrote software for LETE, High Voltage control, Optical BERT

controllers and post processors. Data acquisition using C language.

1994-1995: CUP/MESA project- Responsible for optical cable node control

design. Designed this in Xilinx FPGA and wrote graphical simulator for use

on the PC. Also created a custom made compiler (used YACC & LEX) to make

SONET pattern & waveform as the signal test source for the project.

1993-1994: Worked with LSI Logic Inc. ASIC chip for memory initialization

(memint) which included VHDL design, gate level timing analysis. Also wrote

custom C code: tools, filters, parsers, and memory models to aid in EMSP

reverse engineering (to eliminate Honeywell Corp. design to save $ x105).

1992: Programming DSP16A and XILINX parts for speech processing in the

HANDSOME project.

1991-1992: PSM (Power Supply Monitor System): Designed and integrated the

PSM monitors and logs (onto disk) all events. Other features include:

watchdog for computer sanity check, interfaced to/from commercial alarm

system (ADT corp.) for remote control, totally programmable power supply

control for two power systems (low, high voltage), 7 level user menu

interface (graphical color), all controlled from a remote '386 computer.

1990-1991: THE AUS PROJECT: Filter design, fabricate, program, and debug

two DSP32 digital signal processing boards for undersea cable application.

Board #1 is a TDM multichannel decimation (multistage) digital FIR filter.

Board #2 is a data compressor using TRW's 1024 point FFT as the heart.

1989-1990: Troubleshooting serious software problems with the MATROX

graphics system (screen garbage) and VRTX operating system (computer lock-

ups) used on project ("C" code intensive). Created "tracer" program for

remote in-field debug operations.

ATF (ADVANCED TACTICAL FIGHTER): A major (emergency) troubleshooting

effort on the NIM boards (Optical Network interface) to secure a company

contract win. Other tasks were to analyze clock and signal routing land

failures.

1988-1989: HANDSOME PROJECT: generated software for driving W&G's NPR

noise power ratio test set (HP-BASIC), graphical menu control of digital

receiver chip (HP-BASIC & 64180 uP assembly language).

1987-1988: SBIC (Single Bus time slot Interface Chip): Designed, simulated,

vector generation (functionally & timing). SBIC was prototyped in "laser

logic".

Bell Laboratories (Whippany, Morristown, Murray Hill, N.J.)

MICROELECTRONICS (AREA 52 CHIP DESIGN DIVISION

1986-1987: T7104 (2400 baud) Modem chip: Implemented various logic sub-

assemblies and generated vector sequences to verify (functionally & timing)

all digital logic. Note: this modem chip was very forward looking at that

time!

1985-1986: KSG (Key Stream Generator project) Type I & II: Co-designed and

laid-out in 1.75u CMOS (two ASIC chips) for secure telephone.

1984-1985: MPUP (Multi-Point Upstream Processor): Simulated, and generated

in 2.5u CMOS chip technology and wrote production testing program for

Sentry (Fairchild ) ALGOL automatic wafer & chip tester system.

1983: DF ASIC (Data Formatter for high density mini-recorder): Designed and

simulated transmit section and microsequencer (also wrote table based

assembler for the microsequencer in C).

1981-1983: RANDOM NUMBER GENERATOR (WE catalog device): Designed in

hardware then in software (LSL) polycell circuit language, simulated, wrote

test vectors and Sentry tested 3.5u CMOS ASIC (see patent below).

Bell Laboratories (Whippany, N.J.)

DEPT 2211 COMMON SYSTEMS LAB

1978-1981: CALL PROGRESS SYSTEM (CPS): Designed and implemented both analog

and digital circuit packs for CPS rack for telephone switching offices.

Designed and built two portable (INTEL 8749) microprocessor controlled

automatic test sets for field use (Cadence loop and tone bus testers).

1976-1978: MAGNETIC BUBBLE MEMORY: Support and testing circuit design (for

both Serial & Parallel Bubble Store), and assisted with analog bubble

detector design (These Magnetic bubble modules were forward looking designs

intended to replace computer hard drives with no moving parts)!

AWARDS: Bell Laboratories President's Gold Award Winner 1997

PATENT: 4641102 (1987) Random Number Generator (implemented on AT&T IC #

T7001).

EDUCATION:

1973-1974 Alfred SUNY Chemical Technology

1975 Syracuse University (ESF) Bio-chemistry

1975-1976 Morrisville College, SUNY Elect A.A.S.

1986-1989 Lafayette College

Bell Labs Courses: C language (1-3), Visual C++ & MFCs, VLSI Chip Design,

UNIX OS system, microprocessors (at INTEL ), magnetic bubbles memory

system, Labview, LabWindows, Digital Signal Processing (Oppenheim's MIT

Video courses part 1 & 2).

Local Area Networks (LearningTree course at Washington, DC )

Papers:

Cadence Loop Module Tester (uP based), 12115-0111 Bell Laboratories

Memorandum March 8, 1983

Control Module Signal Path Tester (uP based), 35766-27 Bell Laboratories

Memorandum September 1, 1981

Magnetic Bubble Performance Test System, 20137-3 Bell Laboratories

Memorandum May 2, 1978

Interests:

Loves to hike (the AT), bicycling, huskies and fixing antique jukeboxes.

Other:

Eagle Scout.

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