Project Manager Engineer

Derek Lentz

Box *****

Reno, NV *****

408-***-**** (cell)

email: abmuz7@r.postjobfree.com

EDUCATION

MSEE, Northeastern University, 1976, Boston, Ma.

BSEE, Carnegie-Mellon University, 1973, Pittsburgh, Pa.

PATENTS AND PUBLICATIONS

The patent office has issued 62 patents for which I am the inventor or one of the principal inventors. The patents

are in the fields of CPU design, computer graphics, computer memory systems and computer systems.

EXPERIENCE

My hardware and software experience is extensive and is not completely described here. Most of my experience is in the

design and verification of VLSI chips, which relies extensively on software work. I have designed boards and

implemented designs in FPGA’s. I have used many software tools over the years such as Verilog, VHDL, various

waveform tools, C/C++, perl, shell scripts, make, microcode, assembly code as well as others. I have written and tested a

large amount of software in many languages (mostly C and C++) as well.

Current Project

I am currently designing circuitry for a video product. I will also be writing firmware for this product. This

product uses a number of chips including a large FPGA. I am specifying, designing and testing hardware

modules for the FPGA and assisting in the enhancement of the main circuit board and system.

Magnum Semiconductor.

Engineering Consultant, Design and Verification 12/06-9/08

I designed several sub-modules for a video decoder chip in VHDL. I added functionality to some existing

modules. I performed much of the work to integrated sub-modules into two subsystems that implement the

video processor for the chip. I created testbenches, tests and performed design verification on the modules. I

created a regression environment for the modules and subsystems. I modified and enhanced and tested various

C/C++ reference modules used to verify the design. I wrote a number of perl scripts to automatically generate

VHDL code as well as to generate and interpret test data. I performed various other development tasks as

needed.

ATI Inc.

Engineering Consultant, Design Verification 4/04-12/06

I performed design verification on a number of modules within 9 projects (chips). I wrote perl scripts that

generated tests and analyzed data. I wrote C++ and Verilog testbench code to created testbenches and enhance

existing testbenches. I performed full chip gate-level simulations in 5 projects. The gate level simulations

required extensive efforts to complete since the simulation memory requirements exceeded the virtual memory

available in the computer systems. I assisted in porting Verilog PLI code to a 64-bit CPU platform.

Pulsent Inc.

Engineering Consultant, Video CODEC Hardware Design & Verification 6/02 –1/03

I lead the design and verification of the memory subsystem, which was partially completed when the company

shut down. I worked with the various codec module designers to determine memory requirements. I created a

memory system architecture that would support an enormous number of memory access data streams. I

designed the logic of major components of the system and synthesized them to meet timing requirements. I

verified the operation of portions of the logic. I worked with another engineer to re-architect the memory

controller to allow it to operate with good efficiency.

Desana Systems Inc.

Engineering Consultant, Communications Hardware 10/01 –1/02

I created test benches and performed diagnostics work on logic designed to support TCI/IP communications.

Equator Technologies Inc.

Engineering Consultant, Media Processor 10/99 –6/01

I reverse engineered significant portions of the processor and created engineering documentation for it. I

developed a high-performance memory controller architecture for the next generation of products, wrote a

detailed engineering specification, oversaw the design, worked with a design engineer to implement and tune

the micro-architecture and built a design verification environment to verify the design. I was instrumental in the

diagnosis and correction of several difficult product and system bugs. I modified the data cache design to

significantly reduce its complexity and cost with minimal reduction in performance. I performed system

performance analysis and system performance tuning work. I worked with 2 other engineers to determine the

architectural changes needed to implement MPEG decoding with an achievable clock frequency. I performed

design verification work. I performed a number of other engineering tasks.

3Dfx Inc

Engineering Consultant, 3D Graphics Processor 6/98 –9/99

I developed a test bench and diagnostics for a DDR based memory controller. I integrated the memory

controller and memory models into the full chip test bench. I performed a number of system level diagnostic

tasks.

Macronix Inc.

Engineering Consultant, 3D Graphics Processor Core 9/96 -6/98

I defined the hardware architecture, wrote specifications, implemented and verified approximately 1/3 of the

logic, lead the integration, diagnostics and debug efforts. I developed algorithms for setup calculations, texture

mapping calculations, rasterization. I synthesized all of my design and met the timing requirements of the

project. I provided technical guidance for the project. We implemented some MPEG processing steps in the 3D

core.

Advancel Inc.

Engineering Consultant, 2D Graphics Processor Core 7/96 -1/98

I defined the architecture, wrote specifications, developed tests. I guided the development of the CRTC and the

2D rendering engine. I guided the engineers who implemented both. I provided technical guidance for the

graphics subsystem of the project.

S-MOS Systems Inc.

Engineering Consultant, Several Projects 12/89 -8/96

I designed the architecture of a 3D computer graphics geometry processor, 2D/3D computer graphics rendering

processor for personal computers, a RISC type CPU for specialized applications and a page printer controller.

I wrote detailed functional (architecture) specifications, graphics algorithms and microcode. I worked with

logic, circuit and software engineers to refine specifications. I provided detailed technical direction, solved

technical problems and other issues. I worked with customers to resolve technical issues. I worked with

designers to debug designs. I redesigned and verified (in Verilog) non-functional modules without the aid of the

original designers. I developed simulation and performance tests for the system level simulation. I diagnosed

performance problems in the design and worked with designers to correct them. I debugged system level design

and tests.

I worked with patent attorneys to file and prosecute many patent applications. In addition, I provided a number

of other services as well.

Wyse Technology

Engineering Project Manager, High End PC Graphics 11/87 -12/88

I hired a small team and designed a microchannel based TMS34010 graphics accelerator board with firmware.

We designed 2 ASIC’s and verified them using emulators. The design was completely functional but the market

for microchannel products did not materialize. I saved the company several hundred thousand dollars per year

in their keyboard manufacturing.

American Information Technology

Director, Graphics Development, Architect 6/84 -11/87

I was a founder and the second full time company employee. I was one of several people who built a very

strong development team in the company. I was the architect, project manager and lead designer of a high

performance 2D/3D computer graphics accelerator chip set. I designed 70% of the logic of the 2 chips and

supported the circuit and layout effort significantly. I performed many other technical and management tasks in

the company. I managed the graphics development effort including a team of 7 hardware and software

designers.

Digital Equipment Corp.

Principal Engineer 8/80 -6/84

I was one of 3 senior designers who designed the architecture and designed the DEC GPX-II graphics chip set.

This was a full custom NMOS (HMOS) graphics accelerator chip set for bitmapped graphics terminals. I

designed 60% of the logic of the controller chip and most of the circuit cell structures (except for detailed sizing

and layout). I was responsible for full chip logic verification as well as first pass silicon debug. First pass silicon

was sufficiently functional to build prototypes.

Raytheon Company, Equipment Division, Advanced Development Labs.

Senior Design Engineer 1/73 -8/80

I designed analog, video and digital circuits for the control of LASER systems and the reception and processing

of LASER radiation. I designed, coded and debugged assembly-code firmware for a color weather radar system

display and console (5500 lines of assembly code). I designed and proposed designs for signal processing

algorithms and circuits for radar systems. I designed all electronics except one board for a C02 LASER range

finder. I designed a number of other circuits for signal reception and analysis. I consulted on grounding and low

noise analog and video circuitry and mechanical designs.

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