Engineer Project

LIM JOO SONG

OFFICE ADDRESS: HOME ADDRESS:

INTEL PRODUCT (M) SDN. BHD. 159, Jalan Permai 3

Lot8, Jalan Hi-Tech 2/3, Kulim Hi-Tech Park Taman Desa Permai

***** ***** ***** *****

Kedah, Malaysia Kedah, Malaysia

Phone# : (60)-4- 433-7126/7068 Phone# : (60)-4

Mobile# : (60-16-495**** 484-9519

e-mail: ***.****.***@*****.*** or ********@*****.***

Summary:

Sr. Bios engineer with 8 years plus of experience in Bios/PC Firmware

project and architecture development.

Sr. Microprocessor Test and Product Engineer with 6 years plus of

experience in Microprocessor Test Development, Test Program Optimization,

Process, Cost and Factory Improvement projects.

Skill Set:

Bios Engineering

Architecture: EFI/TIANO (since 2004), Legacy

Intel/AMI Core 8 (since 2002)

Work experience: Project Team Lead, Architect, Baseline

developer, Module

developer, Reference Codes

porting, Product bios development,

Debug, Customer on-site

support, Group operation, First Level

Manager.

Platform: Lynnfield-Clarkdale P55/G55, Nehalem

X58, Atom, Soft SKU,

3 Series, 965, 945, 915, 865,

845.

Modules: Core Baseline, IMC, Chipset, CPU,

PCI, SPI, Fan Control, ACPI,

CSM, OpRegion, ME, etc.

Programming Language: C, x86 Assembly Language, Python Script, C#

Tools: Intel's ITP (In-Circuit Test

Probe), America Arium, various Bios

utility.

Test and Product Engineering

Work experience: Functional Test Program Team Lead, Platform

System

Validation Team Lead, Test

Program development, Platform Test

Suite development, Test

Coverage improvement, Test Time reduction

and optimization, Socket

reduction, User function development, first

Silicon debug at Sort.

Tester: S9000 ATE, Trillium, PC Platform

Programming Language: C, x86 Assembly, Pearl script, VB, Pascal.

Others: Test Methodology, DFT, SBL

Education:

Degree: Bachelor Degree (Hon.) of Electrical Engineering

University Technology Malaysia

Major: Electronics

Graduation: April 1994 (CPA: 3.86)

Language: English, Chinese-Mandarin, Malay, Chinese-Cantonese

Work Experience:

Intel Corporation (Malaysia) :

BIOS Engineer (Jan 2001 to Present)

Microprocessor Test and Product Engineer (May 1994 to December 2000)

Bios Engineer (Board Design Center Malaysia, Intel Channel Board

Division)

Designation: Sr. Bios Engineer (2002-Present)

Responsibility:

Bios Technical Lead and Developer for the BDCM Bios team.

In charge of the next generation platform Baseline and module Architecture

creation, CPU-Chipset RC porting, MRC, Core features development, new board

power up and debug support.

Provide project supervision and technical consultation to internal project

team. Involve in the new project planning and help to drive internal and

external team delivery.

Successfully led the development and deployment of the DX58SO Bios on

Rel8.6.3 baseline. Involved in re-architecting and development of the new

baseline to support the Lynnfield and Clarkdale CPU in single bios.

Pioneering the development of the Intel Upgrade Service board Bios piloted

in 2008. Led the power on effort of the first Intel's Netbook board project

in 2007.

Managed to help Intel won design win from NEC APAC on 845, Korea Trigem on

865, Japan Sotec on 915, Gateway on 925, Philips/ONKYO on 945 and SONY on

965.

Hold the KM Bios team manager position from 2002 to 2005. In charged of the

Bios team operation, hiring and training new bios engineer. Managed to grow

the team capability from projects sustaining to bios module owner.

Switched to technical path in 2006 to focus on Technical Career

development.

Involved in multiple projects assignment in Oregon USA: Oct. 2004 to May

2005 for EFI based TIANO project early involvement, Dec. 2006 to Jan. 2007

on Bear Lake platform development, Sept. 2007 to Nov. 2007 on Q33 Soft

SKU project and Dell power on support in Austin Tx, July 2008 to Sept. 2008

on Nehalem platform development. March 2010 to April 2010 Sandy Bridge

project involvement.

Bios Engineer (Board Design Center Malaysia, Embedded IA Division)

Designation: Sr. Bios Engineer (2001-2002)

Responsibility:

Bios development and support for EID's workstation/server motherboard.

Involved in Chipset porting and Bring Up of the Pentium 4 LP Plumas/ICH3

telecommunication server board for Radisys/Nokia project. Others task

included sustaining the 440BX based server board.

Relocated to Irvine CA under work assignment with Intel's EPSD Bios team to

hand-on workstation/server Bios project from March 2001 to October 2001.

Microprocessor Sr. Product Engineer (Test Manufacturing Group)

Designation: Timna CPU Product/PPSV Team Lead (1999 to 2000)

Responsibility:

Microprocessor Functional Test (S9000 ATE) program owner and factory Team

Lead. Primary tasks include developed, optimized, transferred and

maintaining Timna Functional test program. Involved in Timna first silicon

debug in Arizona's Sort Factory.

Lead the Virtual Factory test coverage and productivities improvement

projects on Socket Reduction, Test Time Reduction, Test Hole resolution,

Bin Split improvement and Speed Path analysis. Manage to hit all the PDQ

requirement and target run rate 1Q ahead of POR schedule.

Lead the cross-site Product Platform System Validation (PPSV) Engineering

Working Group to drive PPSV test suite development and productivity

improvement project. Successfully achieve test time and DPM budget before

HVM.

Key contributor in the GHz product start up task force. Complete the test

program setup and tester qualification within short notice to start up the

GHz product in KM factory.

Designation: Pentium II/III SECC Product Engineer (1997 to 1999)

Responsibility:

Microprocessor System-Test (SysTest) test suite owner and developer. In

charge of developing and creating Pentium III SysTest test suite for

Intel's CPU factories. Pioneer the new Seed-based test suite for platform

validation which became standard format for all latest Intel PPSV test

suite.

Chair the Virtual Factory PE forum to coordinate test suite deployment,

Test Time Reduction project and test coverage improvement activities for

the Pentium III product.

Undergo a total of 12 months early involvement in Santa Clara and Folsom to

develop the SysTest test suite and coordinate factory deployment around the

globe for new product start up.

Designation: i486/Pentium/Pentium MMX CPU Product Engineer (1994 to 1997)

Responsibility:

Pentium MMX Functional test program owner. Responsible in test program

transfer test program from Division to the factory and product

qualification activities. Also own the PC Platform Validation test support.

Involve in test suite enhancement and new test platform startup.

Project engineer for the P54CS Cold Socket Elimination task force. In

charge of unit level failure analysis, new Functional creation, Sort screen

development, Over-Under kill study and documentation. Help Intel to achieve

the first complex microprocessor cold socket reduction project.

I486 CPU product engineer. Responsible for maintaining and sustaining the

I486SX/DX Functional tester program ( in PASCAL ). Involve in low yield and

test failure analysis.

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