Jakisa Radja

**** ***** ****** ****: 972-***-****

Irving, Texas 75063 abmrfk@r.postjobfree.com Cell: 972-***-****

Summary

TECHNICAL MANAGER WITH PROCESS ENGINEERING AND QA EXPERIENCE IN

MULTICULTURAL ENVIRONMENT IN USA, SINGAPORE AND EUROPE. STRONG FOCUS ON

QUALITY, COST, YIELD AND PROCESS MANUFACTURABILITY. HANDS ON LEADER AND

MANAGER WITH ABILITY TO BUILD AND MOTIVATE THE TEAM THROUGH EXAMPLE, TRUST

WITH ACCOUNTABILITY, COACHING AND POSITIVE RE-ENFORCEMENT TO ACHIEVE

RESULTS. STRONG INTERNAL AND EXTERNAL CUSTOMER ORIENTATION, THRIVING IN

FAST-PACED, CHANGING ENVIRONMENTS. SIX SIGMA GREEN BELT.

Key Skills

TECHNICAL MANAGEMENT SEMICONDUCTOR PROCESS MANAGEMENT

SEMICONDUCTOR R&D PROJECT MANAGEMENT

RISK ASSESSMENT CHANGE/RISK MANAGEMENT

PROBLEM SOLVING SIX SIGMA GREEN BELT

PROCESS CONTROL CUSTOMER MANAGEMENT

QMS TOOLS SELECTION AND PROCUREMENT

EXPERIENCE

STMICROELECTRONICS, CARROLLTON, TEXAS AND AMK SINGAPORE 1991- JUNE, 2009

WORLD'S 6TH LARGEST SEMICONDUCTOR MANUFACTURER; $10 BILLION REVENUES.

Process Engineering Manager BEOL-STM, Carrollton (2006-June 2009)

. Lead and develop 14 process engineers and 8 technicians, support

manufacturing, coordinate cross group activities. Manage yield

improvement, cost reduction, throughput improvement and MEMS development

and production. Reporting directly to Process Engineering Director.

. Reduced defectivity 50% by improving process, PM, updating procedures,

leading projects that used FMEA, DOE and other problem solving tools.

. Improved cycle time 20% on CVD process by optimizing process flow using

DOE.

. Reduced machine downtime 5% by introducing automated PM and intervention

qualification BQS.

. Improved Electrical Yield 0.5% by optimization thick Metal deposition

process .

Process Engineering Manager PHOTO-STM, Carrollton (2000-2006)

. Led group of 12 engineers and 8 technicians in supporting manufacturing,

yield improvement, cost reduction and throughput improvement. Reporting

directly to Process Engineering Director.

. Led conversion from C-MOS to BiCMOS manufacturing and successfully

started new technologies and products.

. Changed alignment schemes for several technologies to reduce reject rate

from ~0.5% to ~0.1%.

. Improved throughput 10% and EWS Yield 2% by optimizing wafer layout.

. Achieved cost reduction of $2.4 per wafer by reduction of Photo resist

and developer usage.

Staff Process Engineer PHOTO-STM, Carrollton (1997-2000)

. Build a strong team of 5 engineers and 11 technicians as a hands on

leader.

. Specified new mask aligners: created purchase specification, acceptance

procedures layout of Photo bay and process development. On these tools

80% Photo processing has been done on site after install.

Jakisa Radja

PAGE TWO

STMicroelectronics (Continued)

. SUCCESSFULLY ACCOMPLISHED ASML-CANON MATCHING TO ASSURE SMOOTH TRANSFER

OF TECHNOLOGIES DONE ON CANNON STEPPERS IN OTHER STM SITES. THESE

PRODUCTS COVER 80% OF CURRENT PRODUCTION.

. Directed mix and match among aligners with different field sizes to be

able to utilize older tools for less critical photo steps what increased

effective capacity by 20%.

Process Engineering Manager PHOTO-STM, Singapore (1994-1997)

. Managed Photo process engineering group of 26 engineers in two Fabs.

. Transferred entire Photo module from one FAB to another.

. Improved Photo related WFY losses by 5% by introducing new PM scheme.

. Increased Photo alignment tool throughput 7% by establishing new Photo

mask management.

. Required implementation of problem solving methods like FMEA, DOE, etc.

across Photo module.

Senior Process Engineer PHOTO-STM, Singapore (1993-1994)

. Coached and developed 11 engineers, manufacturing support, cost reduction

and yield improvement.

. Introduced new products and technologies .

. Improved Photo related WFY losses for 5% by optimizing process,

procedures and layout.

. Created tool and process FMEA among the first in ST.

Senior QA Engineer STM, Singapore (1991-1993)

. Supervised 4 QA engineers and 11 technicians. Established In-line

Control, Process Changes System, Metrology Tools Calibrations and

Analysis.

. Resolved several internal customer issues to prevent significant scrap of

3 K wafers.

. Led Introduction of ESD protection system into Fab what improved EWS

yield by 4%.

. Managed project which resulted in reduction of wafer breakage from 3% to

less than 1% yield impact.

RIZ -Zagreb Semiconductors, Croatia 1981-1991

BIPOLAR WAFER FAB AND ASSEMBLY WITH METAL, PLASTIC AND CERAMIC

ENCAPSULATION.

. As a QA Manager successfully led project to qualify line of military

components for Rockwell Collins. At that time RIZ and Motorola were the

only qualified suppliers.

. As a Wafer Test Module Manager led projects to improve yield by ~12%.

Reduced dice sawing process yield loss by optimizing blade cooling, blade

shape and size usage for different wafer types and establishing tester PM

system.

. As a process engineer played vital role in introduction of Ion

Implantation into the Fab. Specified tool, established acceptance and

qualification procedures and led process setup.

Education and Professional Development

MS IN PHYSICS (SOLID STATE PHYSICS), UNIVERSITY OF ZAGREB, CROATIA

DOE, Global 8D, SPC, DMAIC, 6 Sigma, Project Management, Minitab

statistical analysis software

Certifications

CANON ASML ADVANCED APPLICATION COURSES 6 SIGMA GREEN BELT

Citizenship

UNITED STATES

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