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Design Project

Los Angeles, California, 90007, United States
May 28, 2010

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To pursue a career in the field of Electrical Engineering, with emphasis on

RF/Analog circuit design.


Master's in Electrical Engineering

May 2010

University of Southern California, Los Angeles, CA



Graduate Courses:

Mixed-Signal Integrated Circuit Design, Integrated Communication Systems,

Computer Systems Architecture, Diagnosis/Design of Reliable Digital

Systems, VLSI System Design I& II.

Bachelor of Technology in Electronics and Communications

May 2008

National Institute of Technology (REC), Kurukshetra, India

GPA: 8.5/10


Design of Power Amplifier in 0.25um Technology:

The objective of this project was to design a PA at 2.4GHz and Output power

24 dBm. This Amplifier consists of three stages, first two stages are

designed using CLASS B and last stage was designed using CLASS F to

increase the efficiency of power amplifier.

Design of Voltage Controlled Oscillator in 0.25um Technology:

The objective of this project was to design VCO with oscillation frequency

1.8GHz, frequency tuning range > 10%, phase noise at 300KHz difference from

oscillation frequency is <-120dBc/Hz. This component was also used to

generate quadrature signals using concept of injection locking.

Design of an Active Mixer in 0.25um Technology

Jan '09 - May '09

In this project I designed a mixer for with RF frequency 1.8GHz and IF

frequency 1.7GHz. And voltage conversion gain of 10dB and IIP3 > -20dBm.

Design of Narrow Band Low Noise Amplifier in 0.25um CMOS Technology

Jan '09 - May '09

The objective of this project was to design Narrow band LNA with noise

figure 2dB, center frequency of 1.8GHz and gain 20dB. The ASITIC model for

spiral inductors is used which considers various parasitics like capacitors

and resistors during the layout of spiral inductors.

Design of a Wideband TIA in 0.25um CMOS Technology

Aug '09 - Dec '09

The objective of this project was to design Transimpedance amplifier for

fiber optic standard SONET 48 with data rate of about

2.488G-bit/s. Specifications of the design are bandwidth 2.5GHz,

Transimpedance gain of 60dB, Power dissipation 50mW, Total equivalent

input noise current <1uA, Output load 50 Ohms.

Design of an RC Poly-phase Filter.

Aug '09 - Dec '09

The objective of this project was to design 5th order poly-phase filter for

rejection of image frequency. Rejection bandwidth is 3GHz.

Design of a Test Generation System for a FPGA chip (Platform: C)

Aug '09 - Dec '09

The objective of this project was to design test generation system which

consists of three modules- Preprocessor, Fault Simulator, and ATPG.

Preprocessor reads input circuit description and fault list files. And

outputs are pruned fault list and input circuit description with flip flops

removed, this are given to ATPG. ATPG generates test vectors for the given

fault list which are sent to fault simulator for detection report. This

project is handled by team of five people; my part was ATPG module which

was done using PODEM algorithm.

Design of DDR2 Controller using Verilog HDL

Aug '09 - Dec '09

The objective of this project was to design controller which can handle

Scalar read/write, Block read/write, Atomic read/write. Controller is

implemented using Finite State Machine. FIFO's were designed for input data

and input commands. Bank interleaving feature is implemented. Read/Write

commands are issued without auto precharge.

Computer/Programming Skills

Tools : Cadence, HSPICE, Synopsys Nanosim,

Xilinx ISE, Mentor Graphics Modelsim, RF spectre

OrCAD, Assembly Language -8086

Programming Languages : C, C++,Perl

Hardware Descriptive Languages : VHDL, Verilog

Operating Systems : Linux, Windows 2000/XP, Sun


Protocols : PCI, DDR


Grader for graduate level course - Computer Architecture Organization (EE

557) at University of Southern California.

National Institute of Technology, Merit Scholarship recipient for

Excellence in Academics.

Sponsorship for my under graduation from SCCL (Singareni Collieries Company


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