Design Electrical

Anirudh Amarnath Ph: 480-***-****

***, ***** ******* ****, *** # 111, Tempe, Arizona - 85281

*******.********@***.***

SUMMARY of SKILLS

. Experience in Transistor Level CMOS Analog and Digital circuit design,

simulation and layout.

. Proficient in MATLAB, C, C++ programming.

. Experience in Schematic Capture, Simulation, Layout, DRC, and LVS using

Cadence tools.

. Familiar with Digital Hardware Design and testing using Verilog.

. Exposure to Digital Logic Design and Testing in Xilinx ISE and ModelSim

EDUCATION

. Arizona State University, Tempe, Arizona

Master of Science, (Electrical Engineering)

Oct 2009 GPA: 3.63 / 4.00

. Anna University, Chennai, India / Graduated with Distinction

Bachelor of Engineering (Electrical & Electronics)

May 2007 GPA: 8.2 / 10.0

KEY PROJECTS

. Design of a Register file

Spring 2008

o Designed and laid out a 32*32 register file capable of read and

write operations through 2 read ports and 1 write port. The EDP was

calculated on both the schematic and extracted views of the

circuit. The setup was designed so as to achieve a minimum EDP.

Used Cadence for the design, simulation and layout of the register

file.

. Modeling and Simulation of a 3.3V, 10-bit CMOS Pipeline ADC

Spring 2009

o Modeled and simulated the RSD algorithm and designed a 10-bit

pipeline ADC, 1.5 bits/stage having a sampling rate of 80MHz and

achieving an ENOB of 9.04 against 37.7 MHz input. Used Cadence for

the design of the ADC.

. Single Cycle MIPS Processor

Summer 2009

o The project involved the design and testing of a single cycle MIPS

processor with individual blocks coded in Verilog. Blocks included

memory, Register file, Control Unit, Instruction Decoder, Program

counter and ALU.

o Simulations were performed on ModelSim to verify the functionality.

. Design of Single Ended Folded Cascode Amplifier

Spring 2008

o Designed a folded cascode differential amplifier using

Cadence(0.35?m process) for a voltage supply of 2.7V. The amplifier

was designed with a gain of 70dB, unity gain frequency of 26MHz,

phase margin of 68 degrees and a CMRR of 55dB and a slew rate of

10V/ sec and an output swing of 2V.

. Design of Pipeline Simulator

Summer 2009

o Designed a simulator capable of implementing a 5 stage pipeline.

The simulator is capable of processing data transfer, arithmetic,

branch, and meta instructions following a read of source registers

in the second half of the decode stage and writing to register file

in the first half of the write back stage. Used C++ for the

design.

. Design of Cache Simulator

Summer 2009

o Designed and implemented a cache simulator using C++ to implement a

cache capable of performing traces and memory references. The

program takes as input the cache size, block size, associativity,

replacement and write policy.

. Design of Telescopic Cascode Amplifier

Spring 2008

o Designed Telescopic Differential Amplifier for high gain with good

CMRR and PSRR. The Bias voltages were used from a multiplier

circuit. This amplifier was then used in a voltage follower

configuration and slew rate was measured. Used Cadence for design

and simulation of the amplifier.

. Embedded Controller-based Micro Mobile Power Generating System

Dec'06-Apr'07

o Developed a working model of a grid-based Micro-mobile Power

Generator using a bicycle as a prime mover supplying AC&DC loads.

o Used a PIC microcontroller to control the speed, On/Off and

voltage fluctuation in the system.

o Applied "green" principles in design and execution.

WORK EXPERIENCE

. Laboratory aide and Tutor, Arizona State University

Dec'07 - Present

o Tutor undergraduate students in Mathematics, Physics and

Chemistry courses

. Internship at AREVA T&D, Chennai, India

Dec'06 - Mar'07

o Tested SKD Static relays using Master Test Software (MTS)

o Developed programs to create, modify and run automated protective

relay tests (IEEE488 protocols)

. Internship at Shanthi Gears Limited, Coimbatore, India

Jun'05 - Aug'05

o Gained insights into the design and functioning of Geared Motors

and Gear Wheels.

o Exposed to CNC Machine Tool Operations.

RESEARCH EXPERIENCE

. Developed algorithms for optimization of System-on-Chip and Network-on-

Chip. This research was done under the guidance of Dr. Arunabha Sen

(Professor, ASU, Dept of Computer Science and Engineering)

. Presented a Technical paper on "Role of Power Electronic Devices in

Domestic Load" at National Level Symposia.

TOOLS

. CAD Tools Cadence (Spectre, Analog Design

Environment, Virtuoso Layout Editor), ModelSim

. Documentation Tools Microsoft Office, Microsoft Publisher,

Latex, CoreIDRAW

. Operating Systems Microsoft Windows XP/NT/Vista,

Unix, Linux and MAC OS X

. Statistical Tools Design Expert

. Programming languages C/C++, Verilog HDL, HTML, MATLAB

RELEVANT COURSEWORK

Digital Systems & Circuits Advanced Analog Integrated

Circuits Design of Engineering Experiments

VLSI Design Analog-to-Digital Converters Advanced

Silicon Processing

Computer Architecture Semiconductor Device Theory

HONOURS

. Won prizes in Electrical Engineering competitions conducted by the

Society of Electrical & Electronic Engineers, India.

. Won a prize for "Original Thinking" on "Rain Water Harvesting"

project, National Science Congress, India.

. Winner, Best Project Award from the Prime Minister of India,

National Science Congress, India, 1998.

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