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Summary

Broad electrical engineering background with extensive experience in

digital IC IO, high speed interconnects, IC package and PCB (PWB) designs,

modeling, testing and simulations. Expert in addressing signal integrity

issues at chip IO, package and board levels. Skilled in IC physical design

phases (backend processes including schematic capture, layout, functional

verification, ECO, etc) of DSP (Digital Signal Processor) IC designs.

Possessed of strong analytical thinking, troubleshooting abilities as well

as excellent interpersonal communication skills. Dedicated team member with

positive contributions to the assigned R&D projects.

Professional Experience

Electric Design Engineer - ASP DSP Design, Texas Instruments - Feb '01 to

Jun 2009:

- DDR, EMIF, PCI and JTAG IO design, timing and SI simulation and analysis

Focused on chip IO interface designs including package and PC board to

guarantee DSP

chip functionality, performance and specs were met on various customer

boards.

In charge of resolving issues in DSP chip major IO buffer circuit logic

function, timing,

driving strength and SI. Pioneered to deliver IBIS models of DSP IO

driver netlists

to external customers generated through TI Spice simulations.

- DSP chip IR drop, Noise, EM and ESD modeling and simulation

Responsible for creating transistor-level or gate-level IR, Noise, EM

and ESD models that

contain millions of transistors and logic gates. Proficient in

performing SPICE simulations to

generate various electric data that were used for DSP chip final

physical ECOs.

- DSP chip package design, modeling and simulation

In charge of selecting suitable package types for DSP chips with

different core (CPU) clock

frequencies. Proficient in generating DSP IO pin map and generating

package electric

models. Designing system level Spice simulation decks including DSP IO,

package and board

models to resolve any system level SI and PI issues. Responsible for

generating various (2D

or 3D) package IBIS models for external customers.

- High speed interconnects (DDR, SERDES interfaces) design, modeling and

simulation

In charge of DSP DDR interface (near end and far end) timing, jitter and

noise analysis.

Generating eye diagrams by running Hspice simulations for data and

address buses.

Coordinating with SERDES macro design team to implement SERDES macro with

DSP chip

IO rings. Creating transmission line models (in S-parameter format) for

package and board

interfaces with HFSS, which were used for performing system-lelvel Spice

or Spectre

simulations with DSP SERDES interface.

- Package signal integrity (SI) and power integrity (PI) modeling,

simulation and analysis

Creating 3D package electrical models including traces, various vias and

power / ground

planes with package electrical modeling tools (including PakSi-E,

Speed2000, HFSS, etc).

Creating system-level Hspice deck including DSP IO driver, package and

board models

For simulating crosstalk, SSN and ground bounce. Analyzing board-level

PDN dynamic IR

drop and switching noise.

- DSP chip Tester Board and VDB design, modeling and measurement

Creating board level SPICE models (both lumped and distributed) of DSP

Tester board based

on board layout. Involved in DSP chip wafer probing, logic function

testing and IO data

measurement.

Package Electric Modeling Engineer - DSPS Packaging Development, Texas

Instruments - May 1999 to Feb 2001:

- IC package electric modeling tool development using C and C++

Developing and maintaining TI internal package electric modeling tool

called PACED, which

saved over half million dollars for TI to buy equivalent commercial

tools.

- IC package design and analysis flow design and implementation

Integrating IC package design flow with IC chip design flow, which

significantly reduced time-

to-market cycle for new semiconductor IC products.

- IC package electric model library creation

Generating both 2D and 3D package electric models for various IC package

types and

archived them into an online-access library in TI intranet, which were

shared with other TI

design teams.

- Electric lab measurement

Initiated an Electric Measurement Lab that was equipped with Vector

Network Analyzer(VNA),

Time Domain Reflectometry (TDR), Signal Generator, Wafer Probe Station,

Spectrum

Analyzer, Oscilloscope, etc.

Participated in designing and making specific IC testchip boards, which

were used to extract

valuable electric data from packaged ICs through measurement. Performed

intensive lab

measurement on various IC packages with TDR and VNA.

- Commercial IC package electric modeling tool evaluation and

implementation

In charge of evaluating all kinds of commercial IC package and PCB

electric modeling tools

based on capability, robustness, easy-to-use and cost. Studied

feasibility of integrating the

features of these tools with TI internal design, modeling and simulation

flow.

Customer Support Engineer - Ansoft Corporation, Scottsdale, Arizona

July'97 - April'99:

- In charge of customer technical support for semiconductor IC package and

PCB electrical

modeling and simulation tool sets that includes TPA, INDMD, CAPMD, PCB

SI, etc.

- Created various electrical benchmark models with the in-house software

tools. Validated

simulation results against industrial standards and real measured data

from major

semiconductor companies like Intel, Texas Instruments, LSI, Amkor, etc.

- Writing technical white papers, user manuals and training tutorials for

company's software tool

sets.

Technical Skills

- Linux / Unix, Windows XP/NT operating systems

- C/C++, Java

- Mentor Graphics Board Station for PCB Design, PADS and HyperLynx

- Cadence Allegro PCB, APD and Encounter

- HSPICE and TI SPICE

- Ansoft HFSS, Apache PakSi-E, Sigrity Speed2000 and Power SI

- Synopsys VHDL/Verilog, PT, DC,PC, ICC, etc

- Mathworks MatLab, Simulink

- HTML, XML, Javascript

- Agilent ADS, Network Analyzer and Spectrum Analyzer

- Tektronix TDR and Cascade Probe Station

Education

MS, Electrical Engineering, University of Arizona, Tucson, AZ

BS, Electrical Engineering, University of Electronic Science and

Technology, Chengdu, China

Heping Yue

Curriculum Vitae

Phone: 972-***-**** (home), 214-***-**** (mobile)

E-Mail: abmpla@r.postjobfree.com

Address: 3304 Spring Mountain, Plano TX, 75025

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