Profile

Results driven engineer with Project Lead experience. Capable of working

independently and as a member of a team. Seeking a position where I can

most effectively contribute to group objectives. Possess a strong work

ethic, with a sincere commitment to life long technical learning.

Accomplished provider of 100% customer satisfaction.

Professional Experience

INFINEON TECHNOLOGIES NORTH AMERICA, Allentown, PA

Verification Engineer, Mobility Group

12/08- 11/09

. Testing of firmware releases and updates on mobile baseband chipset

. Debug of prototypes and related test hardware

. Full system test and characterization

. Generate test reports for internal and external customer review.

Field Return Applications Engineer, SDARS/Satellite Radio Group

1/08 - 12/08

. Verify failure and perform bench level analysis of semiconductor field

failure returns

. Provide detailed documentation of investigative methods, and a

summarized root cause

. Assist FA team with site selection for emissions testing and die

probe as needed

. Communicate analysis status with customers via teleconference and

email

. Repair test fixtures and associated test hardware

Accomplishments

. Quickly established familiarity with chip-sets

. Eliminated back log of field return queue

. Contributed to closure of a critical qualification issue observed in

next generation release

. Contributed to closing holes in ATE escapes

AMI Semiconductor, Pennsylvania Design Center, Lower Gwynedd, PA

9/05 - 4/07

Analog IC Design Engineer

. Design analog integrated circuits based on customer specifications.

. Verify designs with simulation; pre-layout and post layout extraction.

. Provide design input to Physical Design Engineers as needed.

. Perform laboratory characterization of prototype semiconductor

designs.

. Provide documentation of design as requested (datasheet and

performance characterization).

. Communicate with customers regarding deliverable status and technical

issues.

Accomplishments

. Awarded bonus for design contribution to a project with an accelerated

schedule.

. Successful analog designs in 0.35u and 0.5 u, including a low power 40

MHz crystal oscillator.

Agere Systems (Formerly Lucent Technologies Microelectronics Division),

Allentown, PA 10/00 - 9/05

Analog IC Design Engineer, PLL GROUP, 4/02 - 9/05

. Principal crystal oscillator designer for the group.

. Charge Pump PLL design including multi-phase output and integer

divide.

. Designed custom analog cells for internal and external customers.

. Provided design input to Physical Design Engineers as needed.

. Performed laboratory characterization and evaluation of designs on

silicon.

. Developed functional specifications and datasheets as necessary.

Accomplishments

. Successful designs, in TSMC 90nm and 130nm, that were released to

production.

. Project Leader/Chief Coordinator for a, first time successful, 90nm

Test Chip; comprised of group design and external vendor IP.

. Promoted to member of the technical staff based on technical

contributions in area of crystal oscillators.

. SPOT Award for expedient resolution of a technical issue that was

impeding a production release.

Agere Systems (Formerly Lucent Technologies Microelectronics Division),

Allentown, PA

Standard Cell Library Developer, DIGITAL CELLS GROUP

10/00 - 4/02

. Design, simulation, and physical layout of standard digital cells.

. Design of custom cell requests for internal and external customers

. Characterized cells in existing libraries and provided performance

upgrades as needed.

. Delivered physical and transistor level description files to the

library database.

Accomplishments

. Primary contributor of performance enhancements and offerings in the

company's 160nm standard cell library.

. Significant contributions to standard offerings in the company's first

130nm Standard Cell Library.

IBM, Essex Junction, VT 11/99 - 10/00

Application Engineer, Consumer Segment Division

. Primary technical interface between customer and foundry.

. Provided technical support and resolved problems related to the ASIC

Design Kit.

. Drove schedules for custom deliverables.

. Interfaced with FAE's and Design Engineers to address and resolve

deliverable issues in a timely manner.

. Performed power analysis, simultaneous switching analysis, and signal

integrity simulations.

. Maintained project milestone/issues database.

Accomplishments

. Successfully completed training in IBM's ASIC Design Methodology.

. Based on demonstrated capabilities, received an increase in base

salary three months after start date.

. Consistently performed duties on 7 projects concurrently, with a high

level of customer satisfaction.

ESPEY Manufacturing and Electronics Corporation, Saratoga Springs, NY

1/99 - 10/99

Modeling Engineer

. Evaluated and recommended software for use by Modeling and Design

Engineers.

. Assisted Director of Engineering in preparation of quotes and

proposals.

. Performed Electrostatic modeling and Thermal modeling with FEA

software.

. Performed Electrical Circuit modeling with P-SPICE.

. Principal Investigator for modeling and design of medium density DC-DC

converters using off the shelf components.

.

TLSI, Huntington, NY 9/97 - 1/99

IC Design Engineer

. Design and verification of circuits for custom IC applications.

. Characterized test structures to compare to foundry supplied models.

. Ported core analog cells for process migration.

. Tested and characterized prototype ASICs.

. Assisted in writing ASIC test procedures for Test Engineers.

. Conducted failure analysis of ASICs.

TAD Technical for Harris Semiconductor Power Research and Development,

Latham, NY 5/96 - 9/97

Test Engineer, Power Semiconductor R&D Division

TOOLS:

H-SPICE, LABVIEW, CADENCE (SPECTRE, VIRTUOSO, COMPOSER, ULTRASIM), ASSURA,

MATLAB

MATHCAD, ORCAD (SCHEMATIC, PCB), PSPICE, ANSOFT (MAXWELL), MICROSOFT

OFFICE

Education

State University of New York Institute of Technology at Utica/Rome

Bachelor of Science in Applied Mathematics

May 1997

G.P.A.: 3.36

Bachelor of Science in Electrical Engineering Technology

May 1996

G.P.A.: 3.69

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