Engineer Design

**** ********* ***** ***** 972-***-****

Plano, TX 75074 E-mail

********.*****@*****.**

m

Yuanqiao Zheng

Summary of

Qualifications Proficiency in Magma and SYNOPSYS physical design tools,

and variety circuit simulation tools

Experience in entire chip design flow from cell library

characterization, RTL design, DFT, synthesis, formal

verification, layout, routing, clock balance, timing

closure, to final DRC clean

Experience in high frequency and low power design

Expert level experience in system on chip design, Sonet

and OTN system and chip design, mobile phone chip backend

design

High experience in Perl and TCL language to support

automation

Working knowledge in UNIX, C++ language,systemC, VHDL,

Verilog, Spice circuit simulation

Professional 2009 - 2010 Fiberhome Telecommunication

Experience Technologies

ASIC Design Engineer

Optical transmission Network(OTN) ASIC design

physical design flow setting

2001 - 2008 Texas Instrument

Dallas, Texas, United States

Electrical Design Engineer

Participated mobile phone IC design including Application

processor and radio processor to 0.045 micron

Implemented system on chip physical design from netlist

import, constraint setting, floorplan, power grid

setting, placement, clock balance, routing, timing

closure, ECO, power analyze, final drc clean up, to

subchip handoff

Developed system on chip design flow, which let different

blocks simulation, static timing, and layout working in

parallel and independently for a big chip design

Delivered IP model including ILM, Budget or Real Synopsys

library, timing wrapper, and design data base

Developed fully automatic timing closure flow base on

Synopsys and Magma design tool

Worked on cell characterization and created cell library

1997 - 2001 Alcatel USA Plano, Texas, United States

IC design Engineer IV

Developed ASIC design for products used in Sonet light

wave transmission system

Completed assignments on six ASIC designs, with the

largest chip has gate count up to 2.5 millions

Completed VHDL coding to design Sonet OC192 switch,

overhead process, pointer process, and PLL.

Completed static timing, logic synthesis, Jtag and scan

circuitry synthesis

1996 - 1997 One Multimedia Plano, Texas, United States

ASIC Engineer

Completed ASIC design for products used in video on

demand system. Major function is PCI bus which bridge

8 Mpeg decodes

Completed VHDL coding, logic circuit design, system

verification, circuit synthesis, and tests vector

generation

1986 - 1996 WuHan Research Institute of Posts and

Telecommunications WuHan,

China

Senior Engineer

Served as project leader and chief designer for 155

Mbits/s SDH transport system. The system can handle

digital cross connect at 2Mbits/s level

February 1992 to April 1993, Germany - Participated

German sponsored advanced study, which studies German

telecommunication transport system

Completed 140 Mbits/s & 560 Mbits/s optical communication

system, completed ASIC, FPGA and circuit broad design

Education 1983 - 1986 WuHan Research Institute of Posts and

Telecommunications WuHan, China

MS in Electrical Engineering

1978 - 1982 BeiJing University of Posts and

Telecommunications BeiJing, China

BS in Mechanical Engineering

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