Engineer Design
Resume:
Christopher Cowell
abmo01@r.postjobfree.com
SUMMARY
I am a U.S citizen and a seasoned professional with exceptional analytical
and organizational skills demonstrated by:
* ***** ** ****** networking web development experience
5 years of microprocessor design experience with Intel and ARM
architectures.
2 years of architectural performance modeling for Hyperthreaded and
mobile cores
EXPERIENCE
Faith Bucket LLC - Chandler, AZ December 07 -
Current
Founder/Software Developer
Designed and developed a social networking website using a PHP, Perl, cURL
front end with MySQL support. The site offers social news, interlinked
forum discussions and access to many online sacred texts, translations and
podcasts.
Developed and executed marketing/outreach campaigns that is attracting a
diverse user base with the largest religious affiliations making up 34% of
all users. (20 total religions supported)
Integrated a Facebook Connect application, using FBML, that allow users to
share and engage their beliefs to their Facebook connections.
Added a Recommendation Service that will suggest relevant alternative
viewpoints to active users and/or communities.
Developing Smart Translator Caching plugin that will utilize a distribution
of free translations services without violating timeout period. The website
can support up to 32 languages.
Marvell Technology Group LTD - Chandler, AZ November 06 -
November 07
Component Design Engineer - Global Memory Design Group (acquired from
Intel)
- Delivered Verilog RTL models for the I/D caches for an ARM mobile
core. Performed Formal Verification (FV) and Electrical Rules Check (ERC)
on the compiled memories when transferring a communication processor to a
Marvell/TSMC 65nm process. Successfully converted ERC from a 90nm to a 65nm
process which was a critical automated procedure that checked circuits for
process violations within a custom 65nm TSMC process.
- Designed the clock trees for the I/D cache blocks with documentation.
Oversaw the layout efforts to the mask design team and communicated
foreseeable scheduling and design issues.
Delivered ultra low power compiled memories with drowsy mode support.
Executed circuit validation of memories with ring models that isolated the
proprietary memory cell module delivered by TSMC. TSMC tweaked their memory
cell model to support an old Intel 65nm process that met power goals and
addressed severe critical paths during a technology transfer.
Intel Corporation - Chandler, AZ September 03 -
November 06
Component Design Engineer - Global Memory Design Group
- Design validation lead for a compiled memory audit team. Created and
delegated the DV test plan for the 90nm compiled memories and register
files generated by the Intel memory compiler. Our group took over this tool
from a short-handed team in order to thoroughly validate and fulfill a
release date. Our group continued to support this tool internally for the
next year.
- Delivered a detailed evaluation of the TSMC 65LP compiled memories.
Created/verified a performance database which enabled the group to quickly
determine area, power and speed trade offs for memory transactions within
the Application and Communication products. The database was referenced for
quick prototypes as well as for performance roll-ups by product managers.
Created the power grid model for the memory modules and consistently
delivered IR drop and EM validation updates for each design iteration.
Reported hotspots, weak power nodes and MTTF (Mean Time To Failure)
violations to unit owners and the integration team.
Architecture Performance Engineer - Cellular&Handheld Architecture Team
- Designed and developed an event-based power estimation tool for an
XScale core. Evaluated performance using: memory intensive, floating-point
and DSP algorithmic benchmarks to research low energy mobile architecture
specification. The tool delivered power estimates for functional units,
cache configurations and events, and energy efficient bus encoding schemes.
- Single-handedly collaborated with the floorplan, circuit and
performance modeling team to correlate wire length estimates, power
simulations for each wire and the address/data bus requirements.
Rotation Engineer (REP) - Storage Component Division
(REP targets top 1% recent graduates with advanced technical degrees and
outstanding behavioral skills)
- Delivered a No-touch leakage (NTL) module which is a hardware enabled
component that self-tested I/O pin leakage and return status to the test
engineer. This reduced mass production test time by up to 1ms per part.
- Designed, tested, reviewed and delivered the Verilog/VHDL code along
with documentation. Collaborated with architecture, circuit, process and
product engineers to determine usefulness, level of reconfigurability,
expected I/O pad leakage performance for a 90nm process and a post-silicon
testing strategy for the no-touch leakage block, respectively.
- Quickly ramped up on a new I/O processor and created tests that
validated the memories upon a hard reset. This ensured proper loading of
the bootstrap and correct read/write protection applied to the mapped
memories.
Compaq Corporation - Shrewsbury, MA January 01 -
August 01
Architecture Research Consultant - Alpha Development Group
- Modified the Alpha 21464 performance model to study the effects of
floor planning on interconnect-dependent multi-threaded architecture using
ASIM. Research determined that only memory intensive benchmarks were
somewhat impacted while other by long interconnect delays. These impacts
were restricted to single-core processors.
EDUCATION
University of Massachusetts, Amherst, MA
Master of Science, Computer Engineering, September 2003
Rochester Institute of Technology, Rochester, NY
Bachelor of Science, Computer Engineering, Spring 2000
TOOL EXPERIENCE
Experienced in Virtuoso, Modelsim, ESPCV, TSMC Memory Compiler, Cadence
Toolset, Mentor Graphics Toolset, Spyglass, Assembly IDEs, RCS, CVS
LANGUAGE EXPERIENCE
Verilog, VHDL, Perl, PHP, MySQL, Flash AS3, C/C++, FBML, JSP, CSS, AJAX,
cURL
HARDWARE/PLATFORM EXPERIENCE
Unix/Linux, Windows OS, Solaris, some Altera
PROFESSIONAL ORGANIZATIONS
Semiconductor Research Corporation, NSBE
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