Curtis Peer ***** Jasmine Way

San Ramon, TX *****

Cell: 631-***-****

abmnxi@r.postjobfree.com

Senior Design Engineer

Summary

Senior EIT certified engineer with over 16 years hands-on, full life-cycle

experience in the production of high volume ASICs, microcontroller-based

products and firmware. Results driven with a proven record of on-time and

under budget delivery. Led multiple design and verification teams.

Experienced communicating with all organizational levels.

Technical Skills

Languages: VHDL, Verilog, C/C++, Perl, Assembly, SQL, Java, Bourne Shell

Technologies: Synopsys (Design Compiler, PrimeTime, Formality), Cadence,

Mentor Graphics, SPICE, GNU, Matlab, Visual Studio, RTL and

Behavioral HDL, Synthesis, Static Timing, Formal Verification,

Mixed-mode Simulation, SCAN, JTAG, DFT, microcontrollers,

Altera, IAR

Experience

Embedded Wireless Devices, Pleasanton, CA 2001 - 2009

Senior Systems Engineer

Design, develop, and rollout of ASIC, Circuit board, and firmware for

wireless products. Technologies used: VHDL, Verilog, Perl, Synopsys,

Cadence, ModelSim, RFID, SMNP, Java, SmartCard, Altera.

. Developed simulation environment (Cadence scripts, Verilog behavioral

models, and test vectors) for C1G2 compliant RFID chips for Brazilian

technology partner. Automated T1 measurements to C1G2 spec. Automated

generation of test patterns over I2C.

. Integrated a PCI interface for an ASIC microcontroller allowing for

the creation of a partnership with a large Chinese manufacturer and

entry into the Chinese market. Delivered RTL, synthesis scripts, and

test-vectors.

. Reduced manufacturing costs by 33% of Super I/O to LPC (SouthBridge)

ASIC by converting the 8051 to LPC arbiter from a synchronous, flip-

flop based design to an asynchronous, latch-based design while

maintaining design as synthesizable Verilog RTL.

. Generated $20 million in revenue by designing a SmartCard to LPC

Interface controller. Delivered Verilog RTL for following blocks: LPC

Configuration, Serial IRQ, SmartCard with UART and FIFO. Also

delivered Synopsys scripts, netlist, test-vectors, and FPGA prototype.

Coordinated top-level integration and verification.

Seagate, Milpitas, CA 1994 - 2001

Senior Staff ASIC Engineer

Provided hands-on management for 4 engineers in the design of 5 ASIC mass

storage microcontrollers used by all major computer manufacturers

worldwide. Technologies used: VHDL, Verilog, Perl, Bourne Shell, DSP

Assembly, Synopsys, Cadence, Mentor Graphics, SCAN, JTAG, DFT.

. Reduced manufacturing costs by $3 million by designing and building a

programmable synchronous serial port that supported over 120 different

protocols allowing on-demand vendor changes without additional effort.

Delivered Verilog RTL, Synopsys scripts, netlist, test-vectors, and

DSP firmware for bring-up.

. Increased the performance by 30% of the system test bench for

developing test vectors for validation and verification of the ASIC by

architecting a solution that used a mixed-mode and mixed-language

simulation-bridge. Delivered VHDL behavioral models, VHDL to Verilog

wrapper, and DSP Assembler written in Perl.

. Decreased warranty expenses by $10 million for 3 hard drive programs

by identifying 19 single point failure modes using FMEA techniques and

revising design and production processes to prevent failure modes

resulting in an improved product reliability (MTBF) of 30%.

. Reduced development costs for ASIC programs by implementing metal-

layer-only changes to netlists to remove bugs and support customer

requested revisions. This enabled revisions to be implemented without

impacting customer's production schedule.

. Improved hard drive performance by designing a new burst-sequencer

algorithm implemented in DSP firmware using assembly code.

Integri-Test, Commack, New York 1990 - 1994

Software/Firmware Engineer

Design, developed and supported hardware and software for industrial

automation solutions to control robotic motion, position mapping and

optical character recognition. Technologies used: OrCAD, Altera, Assembly,

C.

. Decreased costs by 50% by architecting a process that integrated

microfilming into a forms scanner allowing customers to maintain legal

requirements of microfilmed copies of forms without separate form-

handling facilities. Delivered: SBus PCB with FPGA, SUN/OS device

driver (in C), and Unix/C library.

. Improved the operation speed by 70% for PCB testing systems by

designing a new algorithm implemented in C and Intel x86 assembly to

remove redundant test points on large nets by comparing capacitance

signatures of known gold boards.

. Decreased the operation cost of PCB tester by designing a position

mapping system that enabled a robot to locate test-points of units-

under-test by searching for capacitance signatures thereby eliminating

the need for an expensive test-fixture. Delivered: ISA PCBs with FPGA,

DOS device driver (in x86 assembly), and DOS/C application.

Devry University, Fremont, CA 2002 - Present

Adjunct Professor of Engineering and Information Sciences

Designed curriculum and taught multiple engineering classes including

. Beginning / Advanced Microprocessors

. Beginning / Advanced Digital Design with VHDL

. Beginning / Advanced Database with Oracle

. Programmable Logic Controllers

University of Phoenix, San Jose, CA 1994 - 2001

Adjunct Professor of IT Technology

Designed curriculum and taught multiple IT classes including

. Beginning / Advanced Programming in C, C++, Java, Visual Basic, SQL

. Beginning / Advanced Software Engineering

. Project Management

. Computer Architecture

Education

Masters of Science in Electrical Engineering, Polytechnic University,

Brooklyn, NY

Bachelors of Science in Electrical Engineering, New York Institute of

Technology, NY

Affiliations

IEEE Active member since 1987

Devry University Adjunct professor for college of engineering and

information sciences

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