Engineer Design

Alexander Grobman

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m: 512-***-****

Performance-driven ASIC SOC/IP Design/Verification Engineer with over 15

years of experience in the design, verification and validation of complex

systems on chip (SOCs) and international experience - lived and worked in

three countries.

Core Competencies:

Digital IP Design Microprocessor VLSI Testing

Architecture

Post Silicon Validation Design Methodologies Configuration &

Debugging

SOC/IP/CPU verification System integration User Support

Technical Background

Verilog, VCS, LEC, RTL compiler, Synopsis synthesis and timing static

analysis tools, Perl, C, Pascal, PLM, UNIX C-shell, PowerPC,

I8051/86, microchip assemblers.

Professional Experience

Freescale Semiconductor, Inc, Austin, TX 2001 - 2009

SOC/IP Senior Design Engineer

. Seventeen automotive flash based SOCs projects in 90/130 nm processes for

power train, communication gateways, breaking, advanced stability control

and automotive radar applications.

. Designed:

- hardware modules (IPs), (e.g. RAM and ROM memory systems with Hamming

Error Correction Code (ECC) and FlexRay communication controller bus

interface unit),

- firmware - SOC boot code, using C and PowerPC assembler languages.

- SOC level verification and production patterns/environment. Used C,

assembler and complex Verilog/C patterns. Designed the C patterns boot

code and methods to compile, build and load these patterns into

microcontroller memories - flash, RAM or external memory models. Used

Perl scripts, make and GNU C compiler tools

Took part in post silicon validation (including power consumption

characterization and analysis).

Designed production patterns to cover test "holes", including for flash

modules.

Total life time revenue from designed products is above $2 billion.

. ROM based ASIC cost reduction version of the flash based dual CPU

microcontroller.

Served as:

- ECC ROM memory system designer developed successful customer code to ROM

content flow, based on internal tool and Perl scripts, with only one mask

layer replacement instead standard 2 layers updates for this technology,

reducing customer code maskset cost by 50%.

- SOC verification leader the project was single revision success and

received the customer recognition reward. Updated M-core, C based

verification environment with more than 700 functional patterns to

support ROM instead of Flash, designed make flow to build and load ROM

image into verilog model, updated several verification patterns to work

with ROM, designed functional verification patterns to test the ROM

system. Several customer code masksets are running now in full

production mode.

. 1.5 M gates video accelerator IP for Advanced Driver Assistance System,

featuring road signs recognition, lane departure warning, adaptive cruise

control support.

Designed two modules:

- The host and debug interface, serving as a control interface for

debugging and host interaction with four internal accelerator

microprocessors. Executed design flow from creating design specification,

RTL coding to synthesis and verification. Created initial verification

environment, including verilog based testbench with drivers and monitors.

- The circle detector, designed to detect circular shapes in the video

frames. Executed design flow from creating design specification, RTL

coding to synthesis and verification. Created initial verification

environment, including verilog based testbench with drivers and monitors,

Perl scripts to build test image patterns

Conducted peers modules RTL reviews, identifying code style improvements,

code and area size reductions up to 50%.

. Serial Peripheral Interface module IP - added several new features,

fixing bugs while maintaining backward compatibility with previous

version. Executed full design cycle in two months ahead of schedule with

no support from previous IP owner. Resurrected testbuilder based C++

verification environment, fixing monitors, drivers and tasks to support

new features. Creating regression scripts in Perl to easy run more than

600 patterns.

Motorola Semiconductor Israel Ltd, Hertzliya, Israel 1994 - 2001

VLSI Design Engineer

. Served as an integral member of the international design team, designing,

developing and engineering MPC5XX family of the highly popular automotive

single chip microcontrollers (with total revenue over $1 billion).

. Developed successful flow for migrating embedded Power PC core design

over several process nodes. Enhanced the core with a new bus interface

unit with real time application code decompression feature, allowing up

to 100% more application code to be stored in the microcontroller

internal flash. Registered several patents on the subject.

. Led a team of 10 engineers in the functional test coverage enhancement of

the MPC5XX microcontrollers. Increased fault coverage from ~50% to more

than 98%, reducing customer return rate to single digit PPM (parts per

million). Developed over 400 functional patterns, written with PowerPC

assembler language. Maintained and updated the embedded PowerPC core

verification environment, including model build and patterns compilation

Perl scripts, random pattern generation scripts, designed verifault

environment for the core patterns stuck at fault grading, including Perl

based scripts to convert tester stimulus to verilog memory based tester

model, extract detected faults lists, create new undetected fault lists,

run simulations, generate reports, visualize undetected faults, drawing

schematics with remains faults.

. Provided MPC5XX parts customer support, helping resolve application

problems.

Ganot Industries Ltd, Netanya, Israel 1991 - 1994

Hardware/Software Design Engineer

. Designed and developed Remote Power meters data collection systems.

. Developed communication protocols for Power Line Carrier networks.

. Designed hardware and software for data collection and front-end units.

. Supported production of military equipment.

Education

Moscow Technical University of Electronics, Moscow, Russia

Master of Science in Electrical Engineering with specialization in

microprocessor systems;

Moscow Technical University of Communications and Informatics Moscow,

Russia

Master of Science in Electrical Engineering with specialization in Radio

communication and broadcasting; Magna cum laude;

Languages: English, Russian, Hebrew. [pic]

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