Engineer Electrical
Resume:
Nalini Kovi
abmn4n@r.postjobfree.com
Summary
Over 5 years of experience in performing pre-silicon and post-silicon
validation, RTL design, integration, verification, synthesis, lint
analysis, formal verification, timing analysis, automation of test flow(s),
test pattern generation, DFT, ATPG, scan insertion, scan chain stitching,
characterization, test cases development, test plan development for mixed
signal SoC using ARM processor and ASIC designs and FPGA.
Technical Skills
Languages VHDL, Verilog, PERL, C and Assembly (ARM, Intel x86)
Scripts Unix shell scripting, Linux, TCL and gmake
Tools Cadence suite RC Compiler, Encounter,
Conformal, NC Sim, Synopsys'
DC Compiler, PrimeTime, GoldTime, ModelSim, Xilinx, Altera.
Work status: EAD
Work Experience
5 years of development experience at Wipro Technologies with senior project
engineer being highest designation. During this time worked as a contractor
at Texas Instruments (about 3 years) and PMC Sierra (about 2 years) client
development centers.
9/2008 - 5/2009 PMC Sierra Burnaby
RTL design and integration of ASIC modules
Senior Electrical Engineer/ASIC
As a design engineer, my primary responsibility is RTL design and
integration of multiple ASIC modules with successful trial synthesis.
Additional responsibilities include co-ordination with verification team
and clients for successful hand-off.
1/2008 - 8/2008 PMC Sierra Burnaby
Lint analysis, Synthesis and Design-for-Test of ASIC modules
Senior Project Engineer/ASIC
As a senior project engineer for synthesis, I was responsible for
performing lint analysis, writing of design constraints, synthesizing RTL,
analysis of the synthesis reports, checking the timing and performing DFT
(scan insertion, scan chain stitching), RAM BIST, ATPG of various ASIC
modules. Lint analysis includes running lint scripts, analysis of reports
and co-ordination with design team as needed.
Formal verification is done in various steps to verify the correctness of
the design.
I was also responsible for successful RTL synthesis, DFT of ASIC modules.
5/2007 - 12/2007 Texas Instruments Houston, TX
Verification of various ARM based TMS470 System-on-Chip
Senior Project Engineer/SOC
As a project engineer, my work involved in verification of various modules
of SoC such as SPI, MIBSPI, ADC, Flexray, DMA, I2C etc and dumping of VCD
on performing gate level simulations, writing of test cases for
characterization and generation of functional TDLS using VCD.
4/2006 - 4/2007 Texas Instruments Houston,
TX
Prototype development using ARM processor
Project Engineer/FPGA
This project involved in integration of RTL and designing of the modules,
performing synthesis and generating bit stream and validating the
performance of FPGA.
7/2005 - 3/2006 Texas Instruments Houston,
TX
Test flow automation, test pattern generation and validation for testing
flash memory modules of TI device TMS470
Project Engineer/SOC
This involved in automation of flow for generating test patterns to test
flash memory by performing various read write operations for the given size
of memory, configuring the registers using ARM assembly.
Using Makefile and Perl automation is done by writing scripts to generate
test patterns and to validate them to deliver to tester team.
9/2004 - 6/2005 Texas Instruments Houston, TX
Post-Silicon validation of ARM based System-on-Chip (TI TMS470)
Project trainee/SOC
This work involved in generating functional test patterns for all the
modules of SoC using value change dump file in parallel to the verification
and the generated test patterns are validated by performing simulation
using SDF and delivered to the PE team to test silicon.
Functional Test Description Language is used to generate Functional Test
vectors.
It also involved debug using oscilloscopes, logic analyzer, code composer
studio.
Additional Skills:
Knowledge in performing layout, DRC, LVS, schematic capture using Mentor
graphics tools,
ARM processor, ASIC design flow, FPGA design.
Knowledge of RF design and Analog design.
Education:
Master of Technology in VLSI Design (awarded gold medal)
Bachelor of Technology in Electronics and Communication Engineering (4 year
degree)
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