Engineer Process
Resume:
Michael M. Orman
Dallas TX ***43
*******@***.***
OBJECTIVE:
A Manufacturing Engineering position, which offers an opportunity to
implement continuous improvement, enhance designs, improve efficiency and
productivity, and increased customer satisfaction and profitability of the
company. Implement new-products, engineer process development, and new
supplier/vendor evaluation.
SUMMARY:
Process/Productivity Engineer with experience in diverse complex wafer
submicron processing. Integral part of 3 wafer size conversions and 3 full
fab startups, including design/project management/startup of Fab in China.
Process and Yield Optimization, Scrap Reduction, Cost Reduction and Yield
Enhancement Champion. Small Team leadership and Project Management. Six
Sigma Quality Green Belt Engineer with 2 institutions.
University degrees in Chemical Engineering and MBA. Supervisory
responsibility since 1995.
- Process Optimization, Development, Lean Mfg - Process, Productivity,
Cpk, 6-Sigma Improvements
- Capital Justification/Equipment Utilization -
Parametric/Electrical Test Engineer
- Line Yield Improvement/Scrap Reduction - DOE/SPC/FMEA/Poka
Yoke/production optimization
- Advanced Equipment Optimization - Project Mgmt. (Fab
Startup/Wafer Size Conversions)
- Improving COO (Cost of Ownership) - Yield Enhancement
(parametric and defect reduction)
- Foundry and Process Documentation/Transfer/Implementation. - Customer
Interface and Quality responses
- Quality Assurance (QA) Auditing and Implementation/ISO9000
Certification/Malcolm Baldridge Quality Award
- CAD (Computer Aided Design) Training at University Level and In-House
EXPERIENCE:
2004 - Present Teccor/Littelfuse LP, Irving, TX
Diffusion/Yield Enhancement /Wet line Senior Process Engineer
. Responsible for 140 Process Diffusion Furnaces, running 4" and 5"
material, 700 to 1275 degrees C.
. Optimized/Implemented Diffusion/Clean processes in New Wafer Fab in
Wuxi, China.
. Processes for doping wafers using Phosphorous, Boron, and Gallium.
. Yield Enhancement: Responsible for 20% Chip Yield Increase by
optimizing/matching
Depositions and Diffusions. Also 15% Yield improvement for new Deposition
processes.
. Responsible for record high Cpk on inline and Electrical Test parameters.
. 5" Transfer Head: Set up area to successfully set up and run 5" wafers,
complete with cycle time characterization and optimization, uniformity
improvements, capital equipment ordering/upgrades.
New 5" process with new processes achieved yields superior to mature 4"
processing line.
. Implemented modified temperature control, resulting in superior process
performance and consistency.
. Spc implementation and Cpk tracking, FMEA analysis.
. Trained and Certified as a Green Belt Six Sigma Engineer. FMEA, DOE.
ANOVA.
. Reduced costs by $70,000/year by replacing destructive testing with
electrical and in-line test.
2001-2004 Dallas/Maxim Semiconductor, Dallas, TX
Diffusion/Chemical Vapor Deposition/Wetline/Preclean Senior
Process Engineer
1. Responsible for all areas of Diffusion/Low Pressure CVD/Atmospheric
PCVD.
2. Development, project management, and startup from scratch of 8" Wafer
Fab. Supervised four Process Engineers and two Technicians. Personally
trained and proficient on all equipment.
3. Determined Vendor and Optimal layout for all Equipment.
4. Brought up full 13,000 ft2 8" Wafer fab. Cycles determined by computer
simulations and short loop analysis, and very first product material
successfully ran with high yield.
5. Resolved 2 severe defect density issues on 8", using short loop
experimentation and advanced defect density scanners. Defect Density
decreased from 3-4 to 0.1-0.2 def/cm2 .
6. Implemented process change in Diffusion resulting in failure rate
reduced from 3000 to < 300 ppm.
7. Implemented full across the board SPC (Statistical Process Control) and
APC (Automatic Process Control) and monitoring, resulting in all Cpk's
inline and at Parametric Test > 1.33.
8. Improved the Line Yield from 84% to > 95 % by SPC control, improved pm's
and processes, documented process control procedures, OCAP's (Out of
Control Action Plans), automation, and dramatic defect reduction.
9. Improved measured Iron concentration in Fab from Mid e 13's to < 1e11.
10. Implemented Process Control, as well are particle removal efficiency
for Pre Cleans.
11. Responsible for 64 advanced semiconductor diffusion furnaces and pre-
cleans.
1995-2001 ST Microelectronics Inc., Carrollton, TX
Staff/Senior Process Engineer, Diffusion/ Chemical Vapor
Deposition /Process Development
12. 100 and 150 mm wafer processing, Horizontal /Vertical Furnaces and
Precleans.
13. Increased Load Size for numerous cycles, improving productivity and
throughput.
14. Set up/developed Low Pressure Deposition Processes with in-situ Phos
doping.
15. Developed Numerous Phosphorus and Boron doping processes, including
reduced pressure process.
16. Doubled load size at critical low pressure deposition process, and
reduced defect density. .
17. Linear Regression Variable Analysis done for process control and
development.
18. Championed line yield improvements that helped Fab go from 86 to 95%
Line Yield.
19. Programming leader of Group for manufacturing software and production
control.
20. SPC champion for group. Trained in Design of Experiments (DOE), Failure
Mode Effects Analysis (FMEA), and 8D problem solving techniques.
21. Brought online numerous advanced equipment and processes, atmospheric
and low pressure.
22. Worked very closely with Design, Advanced Technology, and Device
Engineering to develop new processes.
Diffusion engineer on HP product cross-functional defect reduction team,
ensuring probe yields > 97%.
Education:
MBA, Pepperdine University, April 1995
B.S., Chemical Engineering, University of New Mexico, 1981
Project management classes 2008-2009, Richland College. Enrolled in Project
Management Degree Program
Solid State Electronics Device Courses, Cal State University Long Beach and
UC Irvine
Various other Equipment/Processing/Defect/Yield/Management/Lean
Manufacturing /SPC/DOE training
Certified Green Belt Engineer with two institutes.
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