Electrical Engineer Design

Jayesh D. Patil

*** *. ******* ****** #** ( San Jose, CA 95112 ( 408-***-**** ( (

*********@*****.***

Analog Integrated Circuit Design and Testing

Areas of Focus Include PLL, Op-Amps, ADC/DAC, Power Inverters, and ASIC

Design

Entry-level electrical engineer seeking a fulltime opportunity in the

field of Analog/Digital circuit design & testing.

Technical Skills Summary:

> EDA Tools: Cadence Virtuoso, Synopsys VCS, Eagle PCB, Xilinx ModelSim,

Spice, MATLAB, Code Composer

> HDL: Verilog HDL, Verilog AMS

> Languages: C, Perl, HTML

> Lab Tools: Oscilloscope, Multimeter, Soldering, LabVIEW

> Operating Systems: UNIX, Linux, MS Windows

> Network Tools: Wireshark, Pingplotter

Professional Work Experience:

mPowerSolar ( San Jose, CA Jan 2010 -

Present

Analog Design Engineer

. Designed and tested DC-DC (Push Pull) converter and DC-AC (Hex Bridge)

300W Inverter circuits.

. Designed and tested sense circuits using LM324N Op-Amps for Inverter PID

control.

. Designed automation test bench to test Inverter PCBs in LabVIEW Data

Acquisition System.

. Worked on embedded C programming using TMS320 Microcontroller.

. Performed Spice simulations as well as PCB prototyping.

. Conducted soldering and testing using Tektronix 500Mhz oscilloscope.

Nokia ( Mumbai, India Dec 2006 -

Jan 2007

Field Test Engineer

. Participated in project with CDMA vendors in Indonesia for successful

release of Nokia phones.

. Debugging and error reporting for hardware/software issues for Nokia CDMA

phones.

. Responsible for flashing phones, testing phone features, RF testing, and

capturing error logs.

. Awarded Best Employee for quality field testing in first quarter (Jan

2007-Mar 2007).

eClerx ( Mumbai, India

Nov 2006 - Dec 2007

Technical Writer

. Writing technical web content for Dell Computer

. Writing documentation for software and hardware products that are sold on

www.dell.com.

Bhabha Atomic Research Centre ( Mumbai, India Jun 2005 -

Jun 2006

Engineering Intern

. Programmed a Bluetooth interface in C and designed the PCB using Eagle

PCB designer.

Education:

Master of Science in Electrical Engineering (Dec 2009)

San Jose State University ( San Jose, CA (Major GPA: 3.73/4.0)

. Masters Project: SerDes 6Gbps Clock and Data Recovery Circuit in CMOS

0.13um

Bachelor of Science in Electrical Engineering (Jun 2006)

University of Mumbai ( Mumbai, India (GPA: 3.7/4.0)

IC Design Courses: Mixed Signal CMOS Design, Analog Integrated Circuits,

ASIC Design, High Speed CMOS Design, VLSI Techonologies, Semiconductor

Device Physics

Academic Projects Completed for Masters Program:

SerDes 6 Gbps Clock and Data Recovery Circuit in CMOS 0.13um (Aug 2008-Dec

2009):

. Designed a differential analog front-end comparator and dual loop PLL.

. Used MATLAB and Verilog-AMS at front-end for fast functional simulation.

. Utilized HSpice and Perl scripting for technology characterization.

. Cadence environment for schematic and layout implementation in CMOS 130nm

technology.

7-Bit Flash Analog to Digital Converter (Jan 2009-Apr 2009):

. Schematic design and layout of a 7-bit thermometer coded Flash ADC using

latched comparator in CMOS 130nm for sampling rate of 400Mhz and power

dissipation of 622.56 mW.

7-Bit Digital to Analog Converter (Aug 2008-Dec 2008):

. Schematic design and layout of a 7-bit thermometer coded current steering

DAC for an area of 125umX350um, 800 MHz Clock speed, and power of 600uW in

CMOS 130nm.

32-Bit Multiplier Array (May 2008-Aug 2008):

. Schematic and layout of the core array of a dynamic logic 2 GHz 32-bit

Wallace tree multiplier in 0.13um CMOS.

2-Stage Op-Amp Design with Common Mode Feedback (Jan 2008-Apr 2008):

. Schematic design of a fully differential two stage Op-Amp in CMOS 90nm

with common mode feedback for a gain of 60dB, slew rate of 0.5 X 10^9V/s,

output swing of 0.9V, power of 10mW, and phase margin>70.

4X4 Keypad Scanner Encoder (Jan-Apr 08):

. Design of a 4X4 Keypad Scanner and Encoder in Verilog to interface a

matrix-type 4

Row/Column keypad to an 8-bit input port of a Microprocessor

. Tools used Xilinx Modelsim for Verilog Coding and Synopsys Design

Analyzer for synthesis

Publications:

. J. D. Patil, L. He and M. Jones, "Clock and Data Recovery for a 6 Gbps

SerDes Receiver", accepted at International Conference on Information and

Applied Electronics

Visa Status: F-1 Student on OPT - Start Date: Feb 4, 2010

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