Design Engineer

OBJECTIVE

Seeking a full-time entry-level position as a ASIC Design/Verification

engineer or a DFT engineer.

EDUCATION

Bachelor of Engineering - Anna University, Chennai, India

- June 2008

Specialization in Electrical & Electronics Engineering

-GPA: 3.60/4

Master of Science - University of Southern California

- May 2010

Specialization in Electrical Engineering

-GPA: 3.33/4

RELEVANT COURSES

Digital System Design-Tools and Techniques, Testing of Reliable Digital

Computers(DFT), Computer System Organization, MOS VLSI Circuit Design,

Computer System Architecture, Semiconductor Physics, VLSI System Design I &

II, Modern Solid-State Devices

TECHNICAL SKILLS

Programming Skills : C, C++, VHDL, Verilog, PERL, Assembly

Language programming: 8085, 8086 and MIPS processor

Platforms : WINDOWS (9X, 2000, ME, XP, Vista), MAC, UNIX,

FPGA, ASIC, ePD, MS Office

Simulation Tools : Hspice, DRC, LVS, Simvision,

SimpleScalar

Cadence : Virtuoso, NC-Verilog

Synopsys : Design Compiler, PrimeTime

Xilinx : ISE, ModelSim

Scan Methodologies : JTAG, BIST

Test Equipment : Digital Signal Oscilloscope,

Multimeters, Voltmeters, Ammeters

ACADEMIC PROJECTS

Automated Test Generation System - Design using C++

(Fall 2009)

. Designed and implemented an Automated Test Generation System in C++

which includes components like Preprocessor, Logic Simulator, Fault

Simulator (Parallel and Deductive) and ATPG (D and PODEM Algorithm).

Detection of Single Stuck-at-Faults in a Circuit - Design using C

(Fall

2009)

. Designed a program in C to detect all the single Stuck at Faults using

the concept of Masking, Equivalence, Dominance and Fault Collapsing

(Pruning). Also generated test vectors to determine all the single

Stuck at Faults present in the circuit.

DDR2 Controller - Design and Synthesis using NC Verilog

(Fall 2009)

. Designed and implemented a DDR2 controller in Verilog HDL and

simulated it with Denali's DDR2 model for scalar, block and atomic

read-write operations using Cadence NC-Verilog.

TOMASULO Processor - Design and Synthesis using VHDL

(Summer 2009)

. Designed the various parts of the processor using TOMASULO'S algorithm

and verified in VHDL using Mentor Graphics' Modelsim simulator.

Implemented on Spartan 3E FPGA using Xilinx ISE 9.2.

Pipelined Processor - Design and Synthesis using VHDL

(Summer 2009)

. Designed in VHDL and verified the execution of a 5 stage pipelined

processor using Modelsim simulator and Xilinx to support in order

execution of MIPS instructions taking care of RAW and Branch hazards.

FIFO based interface communication - Design and Synthesis using VHDL

(Summer 2009)

. Designed a dual clocked FIFO based interface with width and depth

expansion using token passing mechanism to communicate between two

systems operating at different clock frequencies in VHDL.

Testing and Improving the CPU Performance

(Spring 2009)

. Tested and improved the CPU performance by redesigning the baseline

processor by changing several micro-architectural blocks and using

Simple ScalarSimulator tool for achieving better MIPS rating by

exploring the design space using simulations.

Error Correcting Code - Design and Synthesis using NC Verilog

(Fall 2009)

. Designed and implemented the encoder and decoder modules for the given

Hamming code using Verilog HDL and synthesized the designed modules

targeted to Oklahoma State University's 0.18um standard cell library.

UART and SPI Protocol - Design and Synthesis using NC Verilog

(Spring 2009)

. Design and implemented the various parts of the UART and SPI protocol

like the transmitter, receiver, master and slave modules using CADENCE

NC-Verilog.

16-Bit Motion Estimator using 4Kb SRAM and Tree Adder - Design and Layout

(Spring 2009)

. Design and layout (including LVS/DRC) of a 16-bit ME comprising of

4Kb SRAM, Data Pointer, 16-bit Absolute Difference & Adder Circuit

using Ladner Fischer Tree Design and Registers was performed in

CADENCE (Schematic/Virtuso).

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ACADEMIC DISTINCTIONS & EXTRA CURRICULAR ACTIVITIES

. Graduated in Electrical and Electronics Engineering with First Class

Distinction and among the top 15 of 120 students.

. Active member of the project HOPE to help the physically challenged

people in Chennai, India.

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