Design Engineer

NHAN D. TRAN

**** *** **** ***., *** Jose, CA *5123/ 408-***-****/

*******@*********.***

Senior VLSI Design Engineer

Physical Design/Circuit Design

Qualifications

Over 10 years of proven design experience with unique background

combining Microprocessors Design with Memory Design in the latest

45nm technology. Areas of expertise include ASIC Design, Physical

Design, and Circuit Design.

. Successfully Composed/Synthesized control and datapath blocks

for Rock Microprocessor from RTL, place and route, Static Timing

Analysis, floorplaning to layout.

. Good exposure to logic synthesis (DC compiler), timing closure

and block level and chip level P&R (ICC)

. Hands on experience with floorplaning, power routing, skew

management, routing (custom/manual routing, shielding),

congestion analysis and resolution, timing optimization, ECO

fixes and RC extraction.

. Good experience in performing logic synthesis, gate level

simulation, noise, power analysis, silicon bring up and ATE test

development (93K and MOSAID)

. Familiar with Static Timing Analysis tool, Power (IR drop and

Electromagnetic checks) and Noise Analysis

. Successfully developed and delivered high-speed (2.3 GHz) SRAM

and Register File blocks in Sun's cutting edge Multithreading,

Multicore Rock Microprocessor.

. Familiar with transistor level design, design rule analysis,

parasitic extraction and Low-Power circuit techniques

. Comprehensive knowledge and experience with submicron CMOS

device characterization.

. Solid knowledge of device physics and ability to use SPICE

simulation and IC design CAD tools

Professional Experience

Intel Corp., Santa Clara, CA 2009 -

2010

Circuit Design/Physical Design Consultant

Develop digital part in ASIC mixed signal chip to validate high speed

Nehalem Microprocessors. The design process includes synthesis,

place and route, timing closure, IR drop and electromagnetic checks

and layout verifications (DRC and LVS).

. Running the whole backend flow from RTL to GDS that includes:

synthesis, placement, clock tree synthesis, routing, static

timing analysis and ECO fixes

. Performing congestion analysis and resolutions, timing closures,

timing optimization and power checks (IR drop and

Electromagnetic)

. Running SPICE on custom circuits to check timing of critical

paths to ensure circuits meet timing specifications

Sun Microsystems, Santa Clara, CA 2003 -

2009

Physical Design

Compose/Synthesis control and datapath blocks from RTL, place and

route, timing analysis, floorplaning to layout.

. Optimizing timing paths and making a trade-off between timing,

area and power

. Performing all tasks from Floorplan, place, route, signal

integrity, power/clock distribution, timing closure, power,

clock and noise analysis and DRC/LVS leading to tapeout

. Hands on experience with floorplaning, power routing, skew

management, routing, congestion analysis and resolution, timing

optimization, ECO fixes and RC extraction.

. Effectively working with all the individual block designers to

fix their respective ends of the timing paths and made

recommendations on various types of fixes

. Using logic/repeater/clock optimization techniques iteratively

to achieve timing convergence before tapeout

. Applying optimization techniques such as clock gating, HVT gate

swap to reduce power

Circuit Design

Develop SRAM and Register File for L2 cache/CPU in ROCK

Microprocessor. The design involves from schematic to transistor

level which includes logic, power, noise and static timing analysis.

. Verifying and characterizing custom circuits using transistor-

level and gate-level simulation tools

. Optimizing circuits to meet Spec. and making trade-off between

speed, area and power

. Performing schematic entry, floorplanning and layout supervision

. Performing timing closure by running Static Timing Analysis tool

and performing Power and Noise analysis

. Running functional verification and fault coverage on custom

blocks

Timing Lead

Part of a team fixing the switch unit's timing of the CPU (interfaces

all the cores with the different L2 Banks). Responsible for fixing

setup and hold violations and managed the timing closure of all the

paths in that unit before tapeout.

. Effectively worked with all the individual block designers to

fix their respective ends of the timing paths and made

recommendations on the various types of fixes.

. Used Logic/repeater/clock optimization techniques iteratively to

achieve timing convergence before tapeout.

Philips Semiconductors / VLSI Technology Inc.., San Jose, CA 1999 -

2003

Memory Development /Library Technology Group

Circuit Design/Characterization Engineer

. SRAM Design: Design SRAM at transistor level which includes

design rule analysis, parasitic extraction, noise, crosstalk and

low power circuit techniques.

. TestChip Design: Design Test Chips to validate the develop

Memory modules. Design flow includes logical and physical

design, simulation, floor planning, physical verification (LVS,

DRC), test vector generation, tape-out, bringup, ATE development

and documentation.

Technical Skills

. Experience with industry EDA tools such as Hspice, Hsim,

Pathmill, Prime Time, Schematic Capture, Layout, Silicon

Ensemble, DC Compiler, ICC, Dracula, Assura, Calibre, Verilog-

XL, Dynacore, Verplex, Innologic, and Debussy.

. Familiar with programming languages UNIX, Perl and C++

Education

San Jose State University, San Jose, CA

Master of Science in Electrical Engineering focus in Circuit

Design

Bachelor of Science in Electrical Engineering: Cum Laude GPA: 3.70

Honors

Dean's Scholar: Commendation for Academic Achievement

National Dean's List

Activities

Member of IEEE since 1999

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