Engineer Engineering

AYYAPPA KARTHIKEYAN

****, ** ****** ****, *** DD*50, Gainesville, FL-32608.

***********@*****.***

Ph: 352-***-****

OBJECTIVE:

To secure a full time position in an electronics company where

acquired skills are applied towards continued growth and development.

Education:

Masters in Electrical and Computer Engineering

May 2010

University of Florida, Gainesville

CGPA: 3.5

Courses: Advanced VLSI, Bipolar IC design, Reconfigurable Computing,

Computer Architecture, DSP, RF systems, Computer Networks, Wireless

Networks, Future of microelectronic technology.

Bachelor of Engineering in Electronics and Communication Engineering

May 2006

Anna University, Chennai

CGPA: 3.6

TECHNICAL EXPERIENCE:

Co-op, Digital Design Team, MIS/HVAL Texas Instruments Incorporated

May 2009 to Aug 2009

Dallas, TX

. Designed digital interfaces in a multi-dye mixed signal chip for a

mobile device.

. Developed DFT compatible RTL for SPI, Real Time Clock (RTC) with dual

alarm, GPIO, PWM and IRQ Interrupt Handler.

. Re-modeled customer source code for Sub-block VID (SVID) to adapt to

the current environment.

Member Technical Staff, Digibee Microsystems Ltd.

June 2006 to July 2008

Chennai, Tamil Nadu, India

. Worked as ASIC design/verification engineer on chip intended for a

mobile phone.

. Designed the AMBA AHB interface of I2S bus.

. Integrated & Verified USB 2.0 OTG, PCM AND RFDI.

Duties involved integrating the module in the SoC, developing test

plan and writing test cases to perform functional and Gate Level

verification.

. Designed a customized behavioral model of the ARM CPU that simulates

poll handling and Interrupt service routines of the different modules

in the SoC.

. Designed a CLOCK ANALYZER model & verified the SYSTEM CONTROLLER in

the SoC

academic projects

. Designed circuit and layout of 8-bit FFT processor and 128-bit SRAM.

. Developed RTL for DES and implemented it on Xilinx Virtex IV FPGA.

. Implemented Voice scrambling in VoIP by encrypting the data using a 64

bit encryption algorithm in an ARM processor to secure the data that

is transmitted.

PROFESSIONAL DEVELOPMENTS:

Accel IT Academy

December 2005 to May 2006

. Pursued training in verilog and was accredited ACCEL CERTIFIED VERILOG

PROGRAMMER.

LEADERSHIP AND AWARDS:

. Received the University of Florida Achievement Award for Academic

merit.

. Managed a National Level Technical Symposium at St. Joseph's College

of Engineering.

TECHNICAL Skills:

Coding Languages : Verilog HDL, VHDL, C, C++, PERL.

Tools : Cadence, NCSim, ModelSim, Xilinx,

MATLAB, Agilent ADS, Clearcase.

Operating Systems : Windows, LINUX.

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