Design Engineer

Naveen Bandi

**** ********* *******, *** # ***, Richardson TX - 75080

Email : ****.*********@*****.***, ******.*****@*******.********.***

Phone : 1-484-***-****

OBJECTIVE

To obtain a Co-op / Full time position.

(Availability: From Summer 2010 )

EDUCATION

. Master of Science in Computer Engineering (Enrolled Fall

2009 - Pursuing)

The University of Texas at Dallas, Richardson, TX

GPA : 3.58/4.00

. Bachelors in Telecommunication Engineering (July-2003 May

-2007)

Viswesvaraiah Technological University (MSRIT), Bangalore, India

GPA : 3.80/4.00

WORK EXPERIENCE TESSOLVE SERVICES PRIVATE LIMITED, Bangalore,

India

. Position: VLSI Test Engineer. (Dec 2007 - Jul 2009)

. Test Platform : FLEX (TERADYNE)

Chips Tested : Power management devices,(Current rating 4-6A)

Single & Dual

Opamp chips.

Others : Knowledge of design of Flex based test

boards & Signal Integrity.

Developed a PERL tool to convert

Verigy test patterns in to Flex test

patterns.

COURSE WORK

. Graduate Level

VLSI Design, Testing and testable design (VLSI), Analog circuits,

Advanced VLSI, Low power VLSI, Computer Architecture, Microprocessor

systems.

. Undergraduate Level

Logic design, Data structures(C, C Signals and Systems, DSP, Power

Electronics,Intel 80x86,VHDL,Computer networks, Operating systems.

Electronic Network analysis

SKILLS

Language : C, C++, PERL, Visual basic, VHDL, Verilog, Hspice, DLX

assembly,8086/8085

assembly.

Tools : Xilinx, Cadence, Synopsys, Tetramax, Modelsim,

PADS, ORCAD, Quartus(ALTERA)

Pspice, Mentor Graphics,IGXL(Teradyne),

RAD51,MATLAB,MS EXCEL,MSVisio.

PROJECTS

. Design of a energy efficient 64bit floating point unit. Most of the

Energy savings were done

on Architectural level of the FPU. Also some gate level energy

optimization techniques were presented, like implementation of XOR

gate using static CMOS and Pass transistor topology.

. Design of low power 15bit floating point MAC, with accumulation

capacity of 10 products, using

IBM 90nm process. In this adder was implemented using sparse -2 tree.

For Multiplier modified

Booth radix-2 was implemented. Also Wallace tree was used to add the

partial products.

. Design and layout of 512bit SRAM using IBM 90nm process (Manual

routing) (16 x 4) 0.5<Aspect ratio < 2. In the Architecture

8 Sense amplifiers (SA) and 8 write drivers (WD) were distributed such

that each word will have 2 SA and 2 WD. Each 4 bit of a word shares 1

SA and 1 WD to make the routing efficient.

. Design of a two stage operational amplifier with gain of 85dB and

power dissipation below 0.6mW.Here miller compensation topology was

used to get a high gain and output voltage swing

with medium power dissipation.

. Design of a Fibonacci series number generator .Synthesized the code

using synopsys, Encounter was used for the routing and final

placement. Functionality check done by Hspice, Prime time used to

determine the critical path.

. Implementation of Boundary scan, BIST, path delay testing, D-algorithm

and its fault coverage.

. Paper presentation with a better way of Resource sharing technique in

Simultaneous multithreading computer architecture. Proposed a method

to statically portion part of the resource and rest to be dynamically

allocated. This will ensure that there is a control over IFQ and ROB

(due to statically portioning).This will also make sure that there is

no under utilization of resource when a thread is idle (due to

dynamic resource allocation).

. Monitoring & Indication of Transmitter status using 8051 Micro

controller (DRDO, India), Design of Patch antenna (meander) using IE3D

software (CAD tool).

. Assembly level programming on Micro controller to transfer a IPv4

packet header and a look up table to its memory and perform

verification of checksum, Calculation of new checksum after reducing

Time to live (TTL) field. Also to search the next destination address

using Look up table.Since Classfull routing is done search algorithm

is based on that.

. Worked on ALTERA NIOS development system to implement a Classless

(CIDR) forwarding engine for IPv4.I used the soft core of NIOS 2 for

the application of packet processing. TCAM was synthesized and then

integrated with NIOS 2 processor to make look up search faster.

. Implemented a Regular expression matching engine using ALTERA NIOS

development system

Using Non-deterministic finite automation (NFA) technique.

AWARDS and ACHEIVEMENTS

. Topped the Viswesvaraiah Technological University in my

undergraduate.

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