Engineer Design

HIMABINDU SAJJA

***** ******** ******* ** ( Austin ( Texas ( Phone 512-***-****(h) (

*********@*****.***

214-***-****(c)

Summary:

. Over 7 years of industry experience in structured hardware

verification, design methodologies, analog / digital circuits,

microprocessor circuits and hardware/software engineering

practices.

. Proficient in verification of complex ASIC chips using Specman

Elite, System Verilog, Vera and VHDL/VERILOG.

. Experience in RTL design and development using VHDL/VERILOG.

. Experience in software languages C, C++ and JAVA.

. Experience in scripting languages PERL, UNIX Shell Script and

Tk.

. Self directed learner capable of climbing learning curve

rapidly. Result oriented and team oriented with excellent

interpersonal skills.

TECHNICAL SKILLS:

Hardware Languages: VHDL, VERILOG

Application/Simulation: PCI, PCI Express.

Synthesis tools: Synopsys, Cadence, MTI, NCSIM, Xilinx,

Aldec, primetime.

Verification Languages: Specman Elite, Synpsys Vera,

System verilog.

Assembly languages: x86, MIPS, ARM

Software Languages: C, C++ and Java.

Scripting languages: PERL, Unix shell script.

Operating systems: Linux, Solaris 5.5.1, UNIX.

Protocols: SONET, TCP/IP, FBD, ATM, CSMB, Ethernet.

EDUCATION:

MS in Electrical and computer Engineering, December 2002,

George Mason University.

Senior Verification Engineer, Qualcomm, TX( 12/07/09 - present)

. Working on verifying UMTS modem for Femto Cell ASIC.

o Working on developing direct-random test cases in Vera for

the verification environment.

o Working on developing functional coverage model for UMTS

modem in System verilog.

o Worked on developing a PERL module to automatically

generate System Verilog covergroups and coverpoints.

. Verified CDMA modem for Femto Cell ASIC.

o Developed verification plans for CDMA modem.

o Developed verification environment for CDMA modem in System

C and Verilog.

o Developed functional coverage model for CDMA modem in

System verilog.

o Worked on debugging various design issues.

. Worked on verifying LTE modem.

o Developed functional coverage model in System verilog for

LTE modem.

o Developed test cases for some of the sub blocks in System

C.

Verification Engineer, AMD, TX (02/20/06 - 011/07/08)

. Worked on verifying CSMB (common socket memory buffer) which is

a new protocol developed by AMD.

o Worked on developing Full chip directed x86 tests to verify

some of the complex parts of the processor in CSMB mode.

o Worked on developing a functional coverage module for the

CSMB.

o Assisted in developing a verification environment for the

CSM Phy.

o Created a Specman EVC for a portion of the verification

environment.

o Worked on debugging the fails from Specman test cases.

. Verified DRAM (DDR2 and DDR3) Controller for single node and

multi core processors.

o Developed Functional coverage module for DDR Bus in C++.

o Developed Perl scripts to collect and analyze toggle

coverage, randomization coverage and functional coverage

data.

o Assisted in debugging various regression failures in RTL

and in DRAM environment.

o Assisted in integrating Micron DRAM model into environment.

Design and Verification engineer for FBD, Intel, WA (02/14/05 -

02/14/06)

. FBD is similar to PCI express and designed based on advanced

memory buffer (AMB) and DDRAM.

o Requirements: verification of FBD modules using Verilog,

C++, Specman E.

o Assisted in design and support of FBD1-AMB and FBD2-AMB

Model sets and Testbenches. Developed some of the test

cases for these models.

o Designed Specman E model for the FBD1-AMB and FBD2-AMB

Model sets for one of the internal customer. Implemented

different direct random test cases in Specman E to test

these models.

o Designed perl scripts to build, run and verify the

results.

o Assisted in implementing programmable Logic interface

(PLI) for the model.

o Worked with Cadence and MTI tools.

o Worked on both internal and external customer support

which included conducting meetings, taking requirements

and implementing them.

ASIC Design Engineer, CNL (06/01/2004- 01/01/05)

. Designed and verified sonet (STS3) framer module for research

laboratory.

o Designed a STS3 framer module in which the payload has

variable size Ethernet packets. The data is sent out on

three different ports corresponding to three STS1 frames.

Three different clocks are generated. VERILOG is used for

RTL Design.

o A test bench is designed in Specman E to verify the STS3

framer module.

o A 150Mhz serial clock is generated.

o The verification plan includes F628(3) pattern checking,

Bit Interleaved Parity checking, Ethernet Packet framing

checking. Full functional coverage is done for the entire

module.

o Perl scripts are designed to compile, run and synthesize

the design.

o Designed a Bus Functional Model for Transmitting serial

data to the framer.

o Static Timing Analysis (STA) flows are generated and

executed for the full chip using Synopsis Primetime.

o Synopsis Design Compiler is used for Synthesis.

Design Engineer, Allegro Networks (08/01/2001 - 03/01/2004)

. Verified sonet (STS1) framer module for a high performance

broadband internetworking multi-router.

o Designed and verified Sonet STS1 framer module.

o VERILOG is used for RTL design and Specman E is used for

verification.

o PRBS pattern generator is designed in test bench to

generate frame data except for first two bytes.

o BIP -8 (bit interleaved parity), which performs even-parity check on

the previous STS-1 frame, is inserted into the B1 byte of STS-1 frame.

o A 100 MHz serial clock is generated.

o The Framed data is verified in test bench for F628 pattern error, BIP

error and error messages are generated for error frames.

o Worked closely with a group that designed PCI Express.

o Gate level simulations are done using Cadence.

o Designed UNIX shell scripts to compile, run and synthesize

the design.

o Static Timing Analysis (STA) flows are generated and

executed for the full chip.

o Cadence tools are used for Synthesis.

. Designed and synthesized an IP diffserve traffic conditioner

ASIC. Specific design highlights include:

o Design of a packet classifier targeted for AFPHB traffic.

Classifies packets and sends on to four different ports

based on differential services (DS) field.

o Design of a two-stage meter based on random exponential

marking algorithm (REM). A price value is calculated

depending on target queue length, present queue length and

previous queue length in both stages.

o Design of a marker that marks the packets in three

different categories based on price value calculated by

meter.

o Design of a Dropper that drops all the non-conforming

packets.

o RTL design and development done in VHDL.

o Hardware level verification is done in Specman E.

Design Engineer, Microwave technologies inc., (08/01/2000 -

07/01/2001)

. Ported the NSA Advanced Encryption Standard codes designed for

ASIC to FPGA using Xylinx. Analyzed and compared the performance

of the codes on FPGA in terms of timing, frequency and area to

that of ASIC. Ported the codes to the different FPGAs- Xylinx,

altera and Aldec. Analyzed and compared the performance results.

. Designed an arithmetic unit capable of performing modular

exponentiation C=ME mod N, where M, N are arbitrary 768-bit

unsigned integers, and E = F4 = 216 + 1. The multiple word

Radix2 Montgomery Multiplication algorithm is used for

multiplication. A 768 stage pipelined organization is used for

design of this algorithm in which each stage is a data path. The

unit was optimized for minimum latency and Area using VHDL.

Design verification was done in Specman E.

Hardware Design Engineer, BEL ltd., Hyderabad India (07/01/1999 -

07/01/2000)

. Designed and implemented decoder logic of the PCS sub layer of

the 10GB Ethernet (IEEE 802.3ae). Specific Design highlights

include:

o The primary goal of the project is to implement the decoder

logic of the Physical Coding Sub layer (PCS) of the

10Gigabit Ethernet.

o Implementation of the three Key State machines Receive

State Machine, Lock State Machine and BER state machine.

o Design of the 64B/66B decoder block.

o RTL coding is done in VHDL. Timing Optimization was done

using Synopsis primetime.

Academic Projects

. Designed a 128 bit Fast adder optimized for minimum delay,

minimum area, minimum product delay*Area in VERILOG. Different

architectures for adders are analyzed and the best architectures

for minimum delay, area and product of delay and area are

determined. A carry look-ahead adder is designed for minimum

delay, a bit serial adder is designed for minimum area and a

carry select adder is designed for product of delay and area.

Design verification in Specman E.

. Compared and analyzed the performance of various cryptographic

algorithms in C++ and JAVA available in public domain. The

performance of algorithms in terms of times of encryption and

decryption are compared between C++ and JAVA. The test is

repeated on various operating systems - Windows98, Unix and

Solaris platforms.

. Simulated and analyzed the performance of decentralized

application replica management protocol called DENO. Simulation

is performed on Solaris using C.

. Designed a constant and a variable rate FIFO. 32-bit wide data

packets were queued in whenever a WRITE signal is high and FIFO

is not full and queued out whenever a READ signal is high and

FIFO is not empty. Used VERILOG for RTL design and development,

Synopsys VERA for design verification and Mentor Graphics for

design simulation. Used debugger for hardware/software

interaction.

RELEVANT GRADUATE COURSES:

VLSI design automation, Physical VLSI design, Introduction

to VHDL, Microwave And Radars, Random Processes in

Electrical and Computer Engineering, Software Construction,

Design and Analysis of Communication Networks, High Speed

Networks, Computer Arithmetic, Cryptography And Network

Security, Operating Systems.

ACHIEVEMENTS:

. First class in my under graduation.

. Educational scholarship during High school and in my

undergrad.

REFERENCES AVAILABLE UPON REQUEST

Contact this candidate