Engineer Design
Resume:
Carl Angstadt
Chadds Ford, PA ****7
abm9d6@r.postjobfree.com
Qualifications Summary
DIGITAL HARDWARE DESIGN ENGINEER EXPERIENCED WITH FPGA/ASIC DESIGN
FROM CONCEPT TO COMPLETION.
In-depth expertise in HDL logic implementation, simulation and
synthesis phases of FPGA/ASIC development. Extensive experience with
clock tree design and related issues.
Excellent problem solving and analytical skills with a consistent
track record for diagnosing complex problems and delivering
effective solutions.
Proven ability to successfully learn new concepts quickly and
complete tasks and projects on time. Excellent verbal and written
communication skills.
Experience
INTERDIGITAL COMMUNICATION LLC
Sr. Engineer 2006-2009
Co-op 2001-2002
Designed and developed hardware required to meet industry specifications
for large-scale ASIC project used in 3G wireless communication. Specific
area of experience include Radio Interface, Data movement, Clocking and
Security/Cryptology.
Analyzed and diagnosed complex issues in simulation, synthesis and lab
environments to achieve quick resolutions to meet tight deadlines.
Directed module verification efforts, designed test plans, created test
regression scripts and reviewed and validated test reports. Oversaw test
team to assure testing completeness and thorough verification of design.
Consistently exceeded objectives and expectations in a process driven
environment.
Unisys
Hardware Engineer 2002-2006
Responsibilities including all phases of device design, development,
documentation, requirements and verification/testing, focusing on
Enterprise Server IO devices, utilizing PCI, PCI-X and PCIe bus
interfaces.
RTL development in both VHDL and Verilog, design simulation, timing
analysis, synthesis, on both ASIC and FPGA projects. Place and Route
targeting Xilinx Vertex2 Pro and Virtex4 FPGAs using Xilinx ISE
tools. Implemented verification plans for large scale Enterprise
Servers in Lab environment to meet product launch schedules on time
and with minimal faults.
Planet Entertainment
Mastering/Maintenance Engineer 1995-2001
Engineer for 24-track recording studio.
Performed all maintenance and repair to enable 24hr. operation of world
class recording studio, including troubleshooting to component level on
analog recording consoles and tape machines.
Technical ExpertisE
HDLS VHDL, VERILOG, SYSTEM VERILOG
Synthesis Synplicity Synplify, Synopsys, Altera Quartus, Xilinx XST
Simulation Mentor Graphics ModelSim, Cadence NCSim, Aldec Active-HDL
Interfaces PCI, PCI-X, PCI-E, AHB
Programming C, C++, Perl, tcl
Education
DREXEL UNIVERSITY - BACHELORS OF SCIENCE-SUMMA CUM LAUDE, COMPUTER
ENGINEER, 2002 DELAWARE COUNTY COMMUNITY COLLEGE -ASSOCIATE IN APPLIED
SCIENCE, ELECTRONIC TECHNOLOGY, 1995
References
AVAILABLE UPON REQUEST
Contact this candidate