Engineer Project

CURRICULUM VITAE

Name : Krupa Shah

Address : Apt #3209, The Isle Apartment, 20250N 67th Ave,

Glendale, AZ - 85308

Telephone : (623) - 236 - 8160

Alternate Phone : (602) - 436 - 6786

Email : abm94e@r.postjobfree.com;abm94e@r.postjobfree.com

EXPERIENCE

Organization : EINFOCHIPS, Ahmedabad

Duration : 4 Years (Including 6 months training period)

Designation : ASIC Verification Engineer

Organization : SYNOPSYS, Bangalore

Duration : 5 Month Contract

Designation : Low Power Verification Engineer

SUMMARY

Expertise in Verification Architecture Design, IP Development,

Debugging Techniques and Project Execution

Hands on Experience of Verification Languages like System

Verilog, Verilog, C++ and System C

Vital Knowledge of Low Power Verification using Synopsys Tools

like MVSIM, NLP and Unified Power Format Technology

Expertise in Using EDA tools like Modelsim (Mentor Graphics),

IUS(Cadense), VCS(Synopsys) as well as other supporting tools like

Simvision, dve, Imanager, ICCR, Clearquest and CRM

Experience of Different Verification Methodologies like AVM, OVM

and CDV

Hands on Experience of various Protocols like AMBA AHB, AMBA

APB, PCI Express, UDP, Ethernet, HSPL(High speed Parallel Link) etc..

Expertise in Scripting using Perl and Shell

Working Experience with different Clients like Synopsys, Mentor

Graphics, Teradyne,

Motorola and Connex

OBJECTIVE

To grow with a progressive company, which will allow me to utilize and

enhance my talents in various challenging technologies.

TECHNICAL SKILLS

Hardware : Verilog HDL and VHDL

Descriptive

Language

EDA Expertise : Behavior/Architectural modeling, IP/Core Logic

Verification, Low Power Verification, HDL

Simulation

EDA Tools : Verilog-XL, Modelsim, VCS, IUS, MVSIM,

NLP, ScriptSim, nWave, dve, Simvision, Imanager

and ICCR

Hardware : AMBA-AHB/APB, HHSPL, PCI, PCI Express, I2C, XAUI

Architectures/ Interface of Ethernet protocol, UDP Protocol, LVDS

Technologies Interface, RISC processors, 8086, 8085 and 8051

Micro Controller,

Low Power : UPF 1.0, UPF 2.0 IEEE Standard

Verification

Programming : C, C++, System Verilog, Verilog, SystemC

Languages

Operating Systems : Linux, Windows-NT, Windows, Windows-XP and DOS.

Scripting : Perl and shell

Languages

Verification : AVM, OVM and CDV Methodology

Methodology

Other Tools : Bugzilla, Rational ClearQuest, Clearcase, CVS,

Perforce and CRM

Management : Worked as Leader of AHB SV VIP Team,

Involved in College Campus Interview as well as

Experienced Candidate Interview for ASIC

Department of eInfochips

Technical : C++, Verilog, Perl, Shell, System C and System

Trainings Verilog

Non Technical : Lagaan Program - Employee Soft Skill development

Training program

Pegasus Training - 1 year training program For

Leadership

PROFESSIONAL PROJECTS

Project - 1 : Verification of Low Power Tools - Synopsys, Bangalore

Duration : 5 months

Technology : Unified Power Format(UPF) 1.0 and 2.0 Standard

Language : System Verilog and Verilog

Tools : MVSIM, MVRC, NLP, VCS 2009.12, DVE, Perforce and CRM

Platform : Linux

Team size : 10

Role : Low Power Tool Verification Engineer

Description : Project involves development and verification of Low

Power Synopsys Tools MVSIM and NLP with respect to UPF

1.0 and 2.0 Technology.

My : Verified Isolation, Retention and Power Switch OFF UPF

contributio Policies for MVSIM and NLP Tools according to UPF

n Standards.

Reported Inconsistencies of MVSIM and NLP Tools'

behavior.

Project - 2 : Verification of Timing Generator Part of SOC Digital

Tester - Teradyne, Boston

Duration : 1.3 Year

Technology : HSPL(High Speed Parallel Link) protocol, HHSPLR (High

High Speed Parallel Link

Raw) protocol, Databus Interface, DDR Interface

Language : System C, C++ and Verilog

Tools : NCSIM(6.2), Simvision, Imanager, Rational Clearquest and

Clearcase

Platform : Linux

Team size : 22

Role : Databus Verification Engineer

Description : Timing Generator is the heart of the digital channel,

implemented in a 90 nm custom mixed signal ASIC. It

contains the logic for 32 digital channels. Timing

Generator ASIC is broken into five major sections:

Vector Generation, Timing Generation, Fail Capture and

Processing, Support logic and Interfaces. The vector

generation has data user inputs for

particular signal pattern. The Timing Generation takes

care for how user timing gets applied to the "vectors".

The Fail Capture and Processing involves in how data

received from the DUT is received, captured and

processed. Databus is used to setup all the control and

status registers in the Timing Generator. This ASIC

supports HHSPLR High Speed Parallel Link Raw) protocol

interface. This interface will run support a

raw transfer rate of 2Gbps. This is implemented as 5-bit

source synchronous bus from the

Source FPGA. Databus contains one framer IP to decode 5

bit interface and other IP to generate inputs for other

block inputs of ASIC.

My : Initial Set Up and automization to make sure all future

contributio Implemented verification Environment Works Properly.

n Maintain HHSPL Transactor and Databus Bypass Transactor,

used to drive Databus Interface of actual ASIC.

Development of Databus reference Model to verify Databus

IP Core logic of Digital Tester. Coverage

Instrumentation of Databus Block and Whole Chip

Implement backdoor path to speed up vector data filling

using external DDR memories. Stress Testing of Vector

Generation Path.

Project - 3 : Verification of UDP to XAUI protocol Converter -

Motorola, Bangalore

Duration : 5 Months

Technology : 12.8 GBPS XAUI Interface of Ethernet Protocol, UDP

Protocol, 800 MBPS Low Voltage Differential

Signaling(LVDS) interface

Language : System C

Tools : IUS 6.1, Xilinx 9.2, Simvision, CVS and Bugzilla

Platform : Linux

Team size : 7

Role : FPGA Verification Engineer

Description : This FPGA serves as to bridge between the Protocol

Engine and the Ethernet Switch. Ingress data enters the

FPGA from the switch on a XAUI interface; the

8b/10b-encoded Ethernet frames are de-coded then

re-formatted so they can be transmitted to the Host

interface. Conversely, egress frames sent by the

Protocol Engine enter the FPGA via a LVDS Dynamic Phase

Aligned interface, are 8b/10b encoded, then are sent to

the switch via a XAUI interface. And also the loop back

testing is there to check complete path, starting from

UDP BFM to Protocol Conversion block to XAUI Loop back

to host interface. This chip is mainly designed for

networking application in which the protocol conversion

block works as bridge for speed maintaining between LVDS

interface which is working on 800Mbps and XAUI Interface

which is working on 12.8 Gbps.

My : Involved in Defining verification environment for

contributio Project. Designed BFM for egress path to inject UDP

n packets on LVDS interface. Designed Host BFM to

configure whole chip registers and also reading the XAUI

frame in case of loop back testing. Verify UDP-LVDS

interface and Host Interface using Random Testcases.

Written the script for Regression and Coverage Point

Instrumentation.

Project - 4 : e-SV Integration of PCI Express evc

System Verilog Transaction Layer

Duration : 2 Months

Technology : PCI Express

Language : System Verilog and 'e' Language

Tools : VCS, Specman, CVS and Bugzilla

Platform : Linux

Team size : 4

Role : Verification Environment Developer

Description : Goal of this Project is to add easiest SV interface to

existing evc of PCI Express containing Phy and Data link

layer.

My : Developed Transaction Layer Model in System Verilog and

contributio connected with evc using General Purpose Verilog

n Interface. Transaction layer can work as Root Complex

and Endpoint. Defined Test plan for Transaction Layer

Sanity Testing of evc with randomized TLPs(Transaction

layer Packet).

Project - 5 : Verification and bring up of parallel processing

Multimedia Chip - Connex, USA

Duration : 4 Months

Technology : PCI, RISC Processor

Language : Verilog, Assembly and perl

Tools : Modelsim, ScriptSim

Platform : Linux

Team size : 12

Role : ASIC Verification Engineer

Description : This chip is mainly designed for audio video processing.

The main idea behind this chip is, the processors must

be encode, decode and transacode multiple channels of

HDTV and require little and no additional silicon than a

custom chip would. PCI master (either RISC processor

model or actual RISC processor) can communicate with PCI

target (PCI core located on chip). Also the PCI core of

chip (DUT) can work as master and access the external

entities like DDR or other peripherals.

My : Responsible for PCI core verification as master and as

contributio target (slave).

n Involved in the verification of cache memory of RISC

processor

Worked for the verification of coprocessor of video RISC

processor.

Project - 6 : AMBA AHB 2.0/APB SV VIP Development and Verification -

Mentor Graphics, CA

Duration : 1.3 year

Technology : AHB, APB

Language : System Verilog and Verilog

Tools : Modelsim, VCS, IUS, CVS and Bugzilla

Platform : Linux

Team size : 5

Role : Team Leader

Description : AHB SV VIP and APB SV VIP are System Verilog based

verification component, which can be integrated with DUT

that incorporate AHB or APB devices. AHB SV VIP verifies

devices that are compliant to AHB 2.0 standard protocol

and APB SV VIP verifies devices that are compliant to

APB standard protocol.

My : AHB :

contributio Defined Verification Environment of AHB SV VIP. Prepared

n test plan and error scenarios for the major components

of AMBA AHB (Ex. Slave).

Verified Slave Component of AMBA AHB SV VIP using

testcases, assertions and checkers. Enhanced AHB SV VIP

as tool independent to work with Modelsim, IUS and VCS.

Initial Maintenance of following AHB SV VIP package:

1) Tool Independent Package (This package supports VIP

simulation on VCS,IUS and Questa tool)

2) AVM methodology Supported Package (This package

supports AVM methodology introduced by Mentor Graphics)

Understood AVM methodology and resolved many bugs

related to AVM package of AHB SV VIP .

AHB SV VIP Usage with AHB Slave DUT and AHB Master DUT :

Verified the AHB slave DUT (AHB2APB bridge) using AHB SV

VIP

Verified master DUT (AHB master transaction model) using

AHB SV VIP

Resolved all the bugs related to Master DUT (Design

related) as well as AHB SV VIP verification environment

related.

Scripting :

Designed generic shell script for system Verilog project

to run Regression.

Script maintains result of system verilog testcases

including coverage merging as well as it is compatible

with all SV supported EDA tools.

AMBA Team Management :

Mentored AHB Team to enhance AHB SV VIP to support Open

Verification Methodology (OVM) and Multilayer AHB

Technology

Mentored APB SV VIP Team to Develop and Verify APB SV

VIP.

Achievements

1 : Leading AHB and APB System Verilog Verification IP Development

Team

2 : Participant of Pegasus(Upcoming Leaders) Program of eInfochips

3 : Selected as Onsite Champion for Synopsys Low Power Verification

Project

Academic Qualification

Examination Discipline / Board/ University Marks %

Specializations

Bachelor in Electronics And Gujarat University 74

Engineering Communication

H.S.C Science Gujarat Higher Secondary 84.89

Board

S.S.C General Gujarat Secondary Board 92.29

Personal Information

Date of Birth : 13th November, 1984

Citizenship : India

Gender : Female

VISA Status : L2 + EAD

Languages : English and Hindi

known

Hobbies : Volleyball, Painting, Dancing, Breaking My own limits

by accepting challenge

Contact this candidate