Project Design

YUNSEN WANG

San Jose, CA

Phone: 408-***-**** (cell); 408-***-**** (home)

Email: abm7od@r.postjobfree.com

OBJECTIVE: A senior position in full/semi custom IC design.

STRENGTH & ACCOMPLISHMENT:

With many year experience in full/semi custom design, I have fully

explored every step of the design process from data sheet

specification, logic and circuit simulation, physical verification,

post layout back-annotation & simulation to chip debugging, which

is resulted many very successful products in IDT (Integrated

Circuit Technology). I can work on any of these design steps or

work on whole chip level design. I am committed to working in a

team environment with the ability to contribute my expertise and

follow leadership directives at appropriate times. I am faster in

learning new tools and employing new design methods in projects, to

improve efficiency and accuracy.

Having served many years in the employ of IDT, I have built-up

serial Dual-Port SRAM (DP-SRAM) products, which range from 5.0v,

3.3v, 2.5v and 1.8v, and from 0.5? down to 0.11? processes, with

particular on 5.0v and 3.3v products which have a full set of DP-

SRAM devices from 1MB density to 64KB density, with IO

(Input/Output) bus width of 18, 16, 9 and 8 bits. Most of these are

still being manufactured in IDT Fabrications.

EXPERIENCE:

7/93-03/09 Principal Design Engineer, IDT, San Jose, CA

SMP (Specialty Memory Product) of FCM (Flow Control Management)

Division

A list of a few projects in IDT

Project: IDT70v27 family - 512KB Asynchronous & Synchronous High-Speed

Dual Port-SRAM. There are 3.3v and 1.8v options with voltage

converter and bandgap regulator on the chip.

Responsibility: As the project design lead, responsible for project

schedule report and the top level floor-plan & wire-plan, logic and

time circuit simulation, AC & DC parameters check, chip level

layout supervision, and physical verification (DRC/LVS). During the

design phase, need checking time parameter margin, signal integrity

and reliability, electro migration effects, signal noise and power

consumption. Also involve chip debugging stage if needed. There is

a patent submitted on this project which I am the primary

applicant.

Project: IDT70v257family - 128KB Asynchronous Low-Power Dual Port-SRAM.

This is our first generation low power DP-SRAM, which target to the

high-end handset cell phone market. This is the highest volume low-

power device sold in the DP-SRAM production line.

Responsibility: As the project design lead, responsible for the

project schedule maintain, top level floor-plan, logic

verification, circuit simulation, and layout supervision, handling

final stage tape-out flow. The biggest issue for this design is

lower power consumption and meets the time specification. During

the design, need checking input and output signal routing and IR

drops, power analysis block by block, signal noise and time

parameter margin checking. Also need consider IDT fab process

sensibility and yield improving, as well as document preparation

for production and chip debugging. There is a patent submitted on

this project which I am the primary applicant.

Project: IDT7028 family - 1MB Asynchronous & Synchronous High-Speed Dual

Port-SRAM. There are 5v and 3.3v, and 64Kx18, 64Kx16, 128Kx9,

128Kx8 option included in this design (a total 32 products use this

design).

Responsibility: As the project design lead, responsible for the

project schedule report and maintain, chip level floor-plan & wire-

plan, logic and circuit simulation, AC & DC time parameter

simulation, power analysis and signal noise analysis, layout

supervision, physical verification, running tape-out flow, as well

as design document preparation for production. Also involve chip

production stage debugging.

Project: IDT70p269 - 256KB Asynchronous Low-Power Dual Port-SRAM. This is

our 2nd generation low-power DP-SRAM device included the power

management concept and the address and IO bus muxed mode.

Responsibility: Perform formal verification with Verilog simulation,

generate randomized logic vectors for simulation with

SystemVerilog, and write the behavior model for the device to our

customers. Handle the chip tape-out flow in the final stage

included DRC and LVS clean up.

Project: IDT70p9267 - 256KB Synchronous Low-Power Dual Port-SRAM. This

is 1.8v low power technology with address and IO bus muxed mode

option.

Responsibility: Perform the chip level floor-planning and AC and DC

time simulation for the memory core section, full chip layout

supervision and final stage verification, full chip back-

annotation/simulation and tape-out flaw handling.

Project: IDT77V500 SWITCHSTAR (Switching Memory).

Responsibility: Responsible for whole chip Place and Route using HLDS

(High Level Design Systems) (floorplan), AutoCells (cell Route) and

MicroRoute (block route).

SOFTWARE SKILLS:

Design tools: SystemVerilog, Verilog, Cadence's Skill, Hercules,

Diva, Dracula, Opus, Hspice, Star-Sim, Star-RC,

Nanosim, TimeMill, PathMill, View Logic.

Programming Languages: C, and C Script, Visual Basic, Visual C++

EDUCATION: M. S. in EE at New Jersey Institute of Technology, Newark, NJ

REFERENCE: Available upon request

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