Software Engineer Design

OBJECTIVE

To obtain a full time/part time position in the field of Digital IC -

ASIC, FPGA Design Engineering.

Experience in FPGA design for applications like video coding systems, ESM

systems in telecommunications; electronic circuit design at transistor

level for analog and digital applications.

WORK EXPERIENCE

Graduate Research Assistant, University of Central Florida, USA.

(Dec 2008 - Present)

Reconfigurable H.264/ AVC Motion Estimation Engine on FPGA:

. Designed hardware scalable architecture for Motion Estimation upto half-

pel accuracy to dynamically support different block sizes, search

ranges, video resolutions and frame rates.

. Implemented the design on self-reconfigurable platform to reconfigure

hardware resources during runtime using the methodology, Dynamic

Partial Reconfiguration.

Software Engineer, VERIZON Data Services, India.

(July 2007-

June 2008)

National Screener-Voice Portal/Call Management:

. Provided key solutions to simplify customer experience through

streamlined screening and self-service menus with the Voice Response

Unit (VRU).

. Analyzed and provided improvements and designed while using VZLogs/Call

Tracker Tool to view integrated logs of the Voice Portal domain.

Electrical Engineering Intern, Bharat Electronics Limited, India.

(Dec 2006-Mar

2007)

Design and Development of Pulse Digitizer Interface for ESM (Electronic

Support Measures) Using FPGA:

. Designed an optimized gate level architecture and developed a VHDL code

for Pulse Digitizer Interface to measure the parameters- Time of

Arrival, Pulse Width, Pulse Repetition Frequency.

RESEARCH PUBLICATIONS

. A Scalable H.264/AVC Variable Block Size Motion Estimation Engine

Using Partial Reconfiguration, Sumedha Gupta K., and Jooheung Lee, In

Proceedings of International Conference on Engineering of

Reconfigurable Systems and Algorithms (ERSA'09), Las Vegas, U.S.A,

July 2009.

. Design of Novel Reversible Carry Look-Ahead BCD Subtractor, Himanshu

Thapliyal and Sumedha Gupta K, 9th IEEE Conference on Information

Technology (ICIT), Bhubaneswar, India, Dec. 2006.

. Self-Reconfigurable H.264/AVC Motion Estimation Design using FPGA

(Under Review).

EDUCATION

Master of Science (Expected-May 2010), Electrical Engineering, University

of Central Florida. GPA : 4.0/4.0

Thesis - 'Reconfigurable Architecture for H.264/AVC Variable Block Size

Motion Estimation Using Motion Activity and Adaptive Search Range'.

Bachelor of Engineering (May 2007), Elec. & Comm. Engg., Osmania

University, India. Percentile : 92

Project - 'Design of Pulse Digitizer Interface for ESM Systems using

FPGA'.

TECHNICAL SKILLS

Languages : Verilog, VHDL, C, C++, Voice XML, HTML.

Tool : Xilinx ISE Foundation, Xilinx PlanAhead,

Altera Quartus, MATLAB, PSPICE, Multisim.

FPGA Devices : Xilinx Virtex2Pro, Altera UP2.

ACADEMIC PROJECTS

MATLAB code for Self Calibration of Stationary Cameras using multiple

images.

Dynamic Partial Reconfigurable Image Filter using FPGA to reduce power,

bitstream size and reconfiguration time.

Analysis and solution techniques for the impact of floating body effect

of PD-SOI on circuit operations and its stability.

Design and performance analysis of digital Phase Locked Loop (PLL) at

transistor level using TSPICE.

ACADEMIC LAURELS AND PROFESSIONAL AFFILIATIONS

Secured 26th rank among 200,000 students in the EAMCET'03 Engg. Entrance

Exam, Hyderabad, India.

. Awarded Prathibha Scholarship by the Govt. of AP, India, for four

years of undergraduate study.

. Student Member, IEEE and Women in Engineering (WIE). (Fall 2008

-Present)

. Organized "Entourage"- an interactive workshop on career development

skills at O.U.C.E.

. Student Placement coordinator for the 2007 Placement Programme - 2007

. Founding member of the college literary club called as 'ERUDITES'.

References available upon request

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