Design Engineer

Ali Minaei

Ph: 602-***-****(cell), Email: ***.******@*****.***

U.S. Citizen

Objective

Searching for a Full time or Contract position in Digital, Analog/Mix-

signal design or Analog/Digital validation/verification.

Skills Summary

I have 12 years experience designing CMOS analog and mixed-signal circuits

such as Reference voltage Regulators, Digital-to-Analog converter, Analog-

to-Digital converters, DLL, Phase Interpolator and Amplifiers. Proficient

in developing Verilog-AMS models for Analog IC Validation and Verification.

Strong knowledge of general CAD tools, SPICE base simulators, mathematical

modeling tools, schematic and layout capture tools and FPGA design tools.

Design experience with FPGA using Verilog on Xilinx's Spartan-3 development

board.

Employment

Design Consultant August 2007 to Present

Currently working on a test project to run a CPU core in the Xilinx's

Spartan-3 FPGA, using Xilinx ISE10.1 to compile the Verilog/VHDL source for

a Spartan-3 FPGA.

Cadence Design System, Porto Alegre, Brazil

Consultant for Cadence Design Center leading a team of ten university

students to successful completion of an Analog Front End (AFE) IC design

using TSMC 130nm process. Responsibilities included:

. Mentoring the students, providing technical guidance and expertise to

design 8-bit SAR ADC, 8-bit R-String DAC, 10-bit Pipeline ADC, Bandgap,

10bit Current DAC, Oscillator and general purpose analog block such as

amplifiers and buffers. Tool and CAD support to the student to complete

their project.

Intel Corporation, Chandler, AZ

Power Management IC Design Division: Worked as a Mix-Signal circuit

designer and validation consultant in Intel's New Business Initiatives

developed high-speed (25-50MHz) multi-phase switching voltage regulator ICs

in an Intel 0.13uM process. Responsibilities included:

. Supported the 10-bit R-String DAC design to use in control loop path.

. Developed Verilog, Verilog-AMS and Verilog-A models for Block-level and

Top-level validation.

. Developed and Supported Chip-level validation test-benches and Behavioral

models for Top-level validation simulations both Mixed-mode (Cadence AMS)

and transistor level.

FreeScale Semiconductor, Chandler, AZ March, 2005 to August 2007

Senior Analog Design Engineer

. Worked on Phase Interpolator for 5Gbits/s Serial I/O using 65nm CMOSSOI

technology. This was a newly developed architecture; responsibilities

include: design a family of Current Mode Logic (CML) circuits such as

Buffers, Latch & Flip-Flops; bias circuit and the Phase Interpolator.

. Supported the design of DLL circuit (1.25GHz) for the Serial I/O;

responsibilities included redesigning some components of the DLL circuit,

circuit simulation, supervising layout, validation and verification.

. Support and delivery of a Phase Interpolator Design for the 1.25Gb/s

Serial I/O; responsibilities included circuit simulations, layout

supervision, validation and verification.

Intel Corporation, Chandler, AZ June, 1997 to February 2005

Analog Design Engineer

. Design/Implementation/Validation & Verification of a 14-bit resistor

string DAC to use as Automatic Frequency Control (AFC) DAC for the

GSM/GPRS chipset. Validated all my units from the top level using

VCS/NANOSIM.

. Design/Implementation/Validation & Verification of a 6-order Biquad Low-

Pass Filter to control the power level of the off-chip power amplifier.

. Designed a control ADC (Cyclic architecture) for the CDMA chipset

product. Tasks included the design of OTA, sample-and-hold amplifier,

comparator, clock generation and digital decoding logic, layout

supervision, and silicon debug and characterization.

. Designed Clock-Reset unit for the Intel Xscale Microprocessor. Tasks

included, custom Logic Design, RTL, layout supervision, silicon debug and

characterization of the PLL circuit and Clock-Reset unit.

. Chip level mix-signal Validation & Verification, developed behavioral

models using VHDL and Saber MAST language for validation & verification

of the image sensor chip.

Arizona State University, Tempe, AZ August, 1996 to June 1997

Graduate Research Assistant for Electronic Packaging lab

1. Modeled an Analog-to-Digital Converter module using Saber's MAST

language and MagiCAD.

2. Assisted with design of Mixed-signal models using Saber's MAST language.

3. Created a Signal-Integrity template for high-speed systems using Saber's

MAST language.

Tools

Experienced with:

. EDA tools: Cadence Design suite: Analog Artist, Spectra, Spectra-RF, H-

Spice, Virtuoso, Path Mill, NanoSim, and ModelSim. Motorola's Mica tool,

Xilinx's ISE, Mentor Graphics FPGA Advantage.

. HDLs: VHDL/Verilog, Verilog-A, Verilog-AMS.

. Programming Languages: UNIX Shell Programming, PERL, Sed/Awk, HTML, C

programming.

. Math Tools: MathCad, MatLab programing, Mathematica.

. Windows: Microsoft Word, Excel, Power Point, Access, Outlook and Visio.

. Xilinx's Spartan-3 development board.

Education

. Additional coursework completed in analog design through Stanford

University.

. Completed course work for the MSEE at Arizona State University.

. Bachelor of Science, Electrical Engineering, University of Alaska,

Fairbanks, AK, August 1995.

Personal

Status: US Citizen.

Hobbies: Mechanical modeling using SolidWorks, Machining, Welding.

Currently modeling a small Stirling engine.

Contact Information

Ali Minaei

3921 W. Dublin St

Chandle AZ 85226

602-***-**** (cell)

480-***-**** (Fax)

***.******@*****.***

Contact this candidate