Engineer Development

Siddharth Saxena

San Diego, CA *****

Email: ********@*****.***

Ph: (M) 1-617-***-****

PROFESSIONAL SUMMARY

. 4+ years of real-time firmware development and testing experience for

multimedia and broadband telecommunication products.

. Experience in firmware profiling infrastructure development for

Qualcomm DSP processors

. Expertise in firmware optimization techniques for MIPS and memory-

footprint

. Expertise in developing logical simulators substituting hardware-

peripherals

. Research experience in signal processing for bioengineering systems

. Experience in firmware build and release systems

. Strong communication skills and an energetic team player

TECHNICAL SKILLS

. Languages: C, C++, Matlab, Assembly(Qualcomm DSP), Trace32 scripts, Linux-

shell scripting, DOS-scripts

. Hardware Platforms: Qualcomm DSP, Motorola 56K

. Compilation and Debugging tools: GCC, GDB, Trace-32, MS Visual C/C++,

Makefiles

. Operating systems: Microsoft Windows 98/XP/NT, Solaris, Linux, Qualcomm

RTOS

. Telecommunication technologies: VDSL

. Source Control and other tools: Perforce, MKS Integrity, MS Office tools,

MS Visio

WORK EXPERIENCE

Engineer, Qualcomm Inc, San Diego, CA

Feb/2008 - Present

Team: Firmware-core team, part of the multimedia systems for mobile phones.

Responsibilities: Integration of various multimedia components, firmware-

image release, firmware-optimization, performance profiling and support of

firmware-images for the Qualcomm DSP (QDSP) chip.

1. Firmware Image Profiling Infrastructure Development

a. Successfully devised an ETM-profiling method that gives highly

repeatable execution counts (MIPS). Reduced variance to 2.5%

down from 20%, making it reliable for use-cases on-target.

2. Firmware-optimization

a. Pioneered effort to integrate higher-layers of firmware with a

more efficient RTOS than the prevailing one thus improving MIPS

throughput (by 10% in some scenarios) as well as memory-

footprint of firmware.

Received acknowledgement for the effort.

b. Reduced boot-up time of QDSP by optimizing memory initialization

code in the BIOS.

3. Fimware test-framework development

a. Successfully configured the QDSP-simulator to accurately match

the performance of hardware in terms of cache-modelling, bus-

latency and processor-clock. This is useful for off-target

testing and profiling.

b. Developed a co-simulator for "Internal-Codec" hardware on Linux

using transaction-level modelling for off-target testing.

c. Co-developed a co-simulator for the "shared memory driver" that

is used for inter-processor communication, useful for off-target

testing of QDSP images.

d. Successfully developed comprehensive stress-test framework for

the "Audio Front End" module.

e. Delivered, in record time, a device driver running on QDSP5000

processor for the SD Card Controller which can be used to unit-

test the hardware.

Received acknowledgement for this work.

f. Successfully delivered unit-test firmware for the Memory

Management Unit that exploits the specifics of the cache-flush

mechanism in QDSP processors.

4. Testing and Release

a. Comprehensive system-level regression-testing and formal-

releases of several firmware images that run on QDSP. Eg. voice-

calls, audio/video codecs over handset/speaker/bluetooth, device-

switching, post-processing, concurrency testing, diagnostic

messages etc.

b. Led effort to modify the build and release procedure to deliver

QDSP firmware source-code to customers as a part of making QDSP

open-source. This involved interaction with "Customer Release

Management" system.

c. Fully developed a PC-based training of "RTOS Abstraction Layer",

including code, the Makfile system and trace32 scripts, for QDSP

customers. This is intended for customers entitled for open-

source firmware.

DSP Engineer, Aware Inc., Bedford, MA

Sep/2005 - Nov/2007

Team: VDSL (Very high bit rate Digital Subscriber Line) team.

Responsibilities: Firmware development, testing, support and maintenance of

VDSL modems supporting the ITU-T VDSL2 standards.

1. Multiport modem bring-up and firmware development

a. Successfully configured and tested, in simulation, a "hardware

acceleration core" that is responsible for cyclic-extension,

windowing, filtering and equalization over 4 modem-ports

simultaneosly.

b. Successfully brought up, in simulation, frequency-domain

loopback of a new multiport modem. This enabled several modem

functionalities like constellation encoding/decoding, freq-

specific gain-scaling, FFT/IFFT.

c. Significantly improved MIPS efficiency of the controlling

processor by moving expensive algorithms like "power-spectral

density", "signal-to-noise ratio" "vector-power","carrier tone-

reordering" etc. from the processor to a "hardware accelaration

core".

d. Prototyped, in software, design of frequency-domain equalization

hardware using LMS and signed-LMS approaches. Compared the two

prototypes in terms of SNR and convergence- time.

2. Testing of single-port modems

a. Maintained simulation-based regression tests for modem firmware

checking for CRCs and FECs, and hardware-based regression tests

that generated "data-rate" over "loop-length" statistics.

b. Successfully delivered pass/fail test-scripts that check for

CRCs and FECs. Used these scripts to simulate CRCs and FECs and

test functionality of "modem performance layer".

Research Assistant, Institute of Sensory Research, Syracuse University,

NY Jan/2005 - July/2005

1. Incorporation of temporal adaptation in the inner hair cell of an

auditory nerve model

a. Successfully simulated, in C++, the "Inner Hair Cell"

component of the auditory periphery.

This consisted of a "transduction non-linearity" and a "time-

varying low-pass filter".

b. Incorporated the above component in the MATLAB-based model of

"Auditory Periphery".

c. Stress-tested and analyzed the new "Auditory Periphery" model

in terms of impulse and frequency responses to "pure-tones"

and "sinusoidally amplitude modulated" stimuli. Demonstrated

close correlation of the results with empirical data.

ACADEMIC PROJECTS

. Sound classification using artificial neural networks, Syracuse

University, 2005

. Linear predictive coder for speech, Syracuse University, 2004

. Implementation of an FIR zero-forcing channel equalization filter for

a wireless LAN link, Syracuse University, 2003

. Hindi Language localization of palmtops, Pune University, 2002

EDUCATION

M.S in Electrical Engineering, Syracuse University, Syracuse, NY

GPA: 3.9 CGPA: 3.82

Specialisation in Digital Communications and Digital Signal Processing,

July 2005.

Diploma at the Centre for Development in Advanced Computing (CDAC),

Bangalore, India

Diploma in Embedded System Design, Aug 2003

B.E. at University of Pune, India

CGPA: 3.26

Bachelor of Engineering in Industrial Electronics, June 2002

AFFILIATIONS AND ACTIVITIES

. Phi Beta Delta honour society for international students (01/04 -

01/06).

REFERENCES

. Available on Request

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