Engineer Manager

Wojciech Worwag

***** ******* ****.

Fremont, CA 94538 Cell: 505-***-****

Email: ********.******@*******.***

PROFESSIONAL PROFILE

> Recognized expert in wafer factory HVM plating operations

> Demonstrated significant technical leadership in emerging materials in

solar technology including:

o Conductive Adhesive for interconnects in solar modules;

o Chemistry of Diffusion Barrier paste for Emitter Wrap Through (EWT)

solar cells.

o EPI reinforcement and Lambertian coatings in thin film solar cells.

> Identified Saw Damage Etch (SDE) improvements to increase solar cell

efficiency

> Builds, leads and influences international teams toward development of

strategic materials in solar cell technology. Proven team building record

with European and Asian scientists and engineers. Innovative and

creative professional.

PROFESSIONAL EXPERIENCE

SENIOR DEVELOPMENT ENGINEER

10/2009 - Present

SOLEXEL, Inc.

Milpitas, CA

Joined Solexel Inc. a startup company, as a development engineer with

direct responsibilities in:

1. Reinforcement of Si very thin layers,

2. Reliability of cell and module components

3. Development of metallization solutions in solar cells

SENIOR DEVELOPMENT ENGINEER 09/2008 - 09/2009

Advent Solar, Inc.

Albuquerque NM

Joined Advent Solar, a startup company, as a development engineer with

direct responsibilities in:

1. Conductive Adhesive development in the Module Assembly,

2. Saw Damage Etch process ownership

3. Diffusion Barrier chemistry formulation and optimization.

. Led and directed European supplier and Advent Solar engineering in

conducting research on 20+ years of data on moisture importance

modulating Conductive Adhesive (CA) properties

. Drove CA development with major Japanese CA supplier. This resulted in

successful formulations of a price competitive and reliable new

interconnect material.

. Assumed ownership of SDE and PSG modules. Drove SDE development

through DOEs to improve Solar cell efficiency and line throughput.

. Identified main components of Diffusion Barrier paste, a critical

material in EWT solar cell technology, and initiated research to

prevent excursion in this process. Engaged a major Japanese supplier

for development.

MANAGER/ SENIOR MATERIALS ENGINEER January 2004 - August 2008

Intel Corporation

Chandler, Arizona

Transferred to Assembly Technology Development at Intel Corporation as

development engineer in STRL group. Promoted to Manager in result of

the achievements in Thru-Silicon-Via technology. Transferred to the

Materials Group at ATD in charge of supplier development and management

in USA and Asia.

. Led developments on electrochemical phenomenon in Carbon Nano-tubes

plating in applications for thermal solutions in CPU technology.

. Led Internal Heat Spreader development with domestic, Chinese and

Japanese suppliers. Enabled development of new thermal CPU solutions

in chip assembly.

. Project Leader for Optical Interconnects Development international

team (Israel-USA). This was a successful project in identifying high

speed alternative to copper interconnects.

. Led Thru-Silicon-Via successful development in sputtering and plating

operations. Achieved manufacturing readiness in Semitool plating

tools. Worked with and coached Japanese co-workers and suppliers.

SENIOR PROCESS ENGINEER May 2000 - December 2003

Intel Corporation

Hudson, Massachusetts

Joined Intel Corporation as a back-end process engineer with

responsibilities in C4 and Copper plating. Direct responsibilities for:

1. Process technology transfer and sustaining,

2. Test wafer regeneration,

3. Defect excursion prevention development.

. Key team member for new silicon factory startup and technology

transfer from Oregon PTD to F-17 Hudson, MA.

. Owned C4 and Cu plating operations, and excursion prevention

development.

. Focus on test wafer regeneration and cost reduction. This generated

over $3,000,000 savings per year.

. Champion of back-end defect reduction and defect metrology.

SENIOR ADVISORY ENGINEER

1992 - 2000

Seagate Technology Inc.

Bloomington, MN

. Formulated and implemented Pd-Ni plating solution in High Volume Wafer

manufacturing.

. Owned international Au plating process transfer from USA to Ireland.

. Responsible for plating process development in Magnetic Heads Wafer

factory.

. Managed thin film metrology: XRF/XRD Auger, FIB/SEM and TOF-SIMMS.

Process Control and Formulation Chemist

1988 - 1992

Epner Technology Inc.

Brooklyn, NY

. Formulated and implemented Gold and Nickel (EN) plating solutions.

. Responsible for control of plating process : Nickel, Gold Copper, Tin,

Tin-Lead

. Responsible for gold recovery operations

. Management of Waste Water Department

Education

Doctorate Degree in Chemical Engineering

Technical University of Wroclaw, Poland

Dissertation on kinetics of KNO3 in MSMPR mass crystallizer,

multidimensional Population Balance kinetics modeling.

Training & Relevant Coursework

Six Sigma Green Belt with Minitab training

DOE training with JMP

Oracle System and Database

Workstream, SAP, Microsoft Office

First Level Manager and Microinequities training

Project Management, Kepner-Tregoe training.

Technical Knowledge

American Electroplates and Surface Finishing Society certified instructor

Programming in FORTRAN, Turbo Pascal and C/C++.

Other Information

Languages: Fluent in English and Polish; passive Russian.

Open to relocation (US or global)

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