Engineer Design

***** ******* ***** #***

San Diego, CA ***** Nameeta Patil Ph: 517-***-****, 858-***-****

ablmzh@r.postjobfree.com

www.linkedin.com/in/nameetapatil

Objective

I am seeking a challenging position that will provide opportunities for

growth and personal development and also allow me to apply my skills and

expertise.

Summary

. 2.5 years of start-up experience in RTL design, functional verification

and synthesis.

. Expertise in designing and debugging modules using Verilog, VHDL and

System Verilog.

. Proficient in using various industry tools like ModelSim and VCS and

Matlab

. Have hands on experience with Xilinx's FPGAs and ISE tools.

. Exceptional interpersonal, communication and presentation skills.

. Excellent capacity to multitask; manage numerous, often competing

priorities and thrive in dynamic environment.

. Demonstrated ability to work independently as well as be a decisive team

player.

Professional Experience Aug 2005 - Nov

2007

Redpine Signals Ltd. Design/Verification Engineer

. Proven success in coding a FSM (Verilog) for I2C bus.

. Created a test environment in Verilog for functional verification of the

I2C bus module and the SPI and UART modules at block and system level.

. Verified the functionality at sub-system level with APB and AHB bus

interfaces

. Experienced working with DC synthesis to synthesize the RTL.

. Performed preliminary testing of the design on a FPGA.

. Coded the firmware in C language for peripherals like GPIO, SPI and UART.

. Developed regression test scripts for testing and DC synthesis for the

design.

. Experienced working with direct C to interface C functions into Verilog

test bench to functionally verify security engines like SHA1, AES, and

DES.

. Developed in-depth documentation for user manual for the complete chip

including various modules like inter-thread interrupt controller, random

number generator, Semaphore, I2S and PLL.

. Completed a detailed research on how an EDE1144 and 74C922 keypad encoder

IC's can be used with Redpine's LAN chip for interfacing a 4x4 keypad.

. Provided strong contributions as a key member of the review team to

effectively review various work products.

. Organized and facilitated knowledge management by mentoring new team

members and creating knowledge documentation.

Technical Skill Set

Language: Verilog/VHDL, System Verilog, C, TCL

Simulator: ModelSim, Synopsys VCS, MATLAB, Xilinx ISE,

ChipScope

Platform: Linux, UNIX, Windows (9X/2000/XP)

Synthesis Tool: Synopsys Design Compiler

Other Tools: CVS, BugZilla, MS Office (Word, PowerPoint, Excel,

Outlook)

Bus Interfaces known: I2C, SPI, AHB, APB, PCIE, I2S

Protocols: 802.11, Bluetooth

Education

. Integrated Circuit Design Engineering Certificate (2008 -

Present)

University of California, San Diego Extension

. Bachelor of Engineering (Electronics and Comm.) - Osmania University,

India (2005)

References: Available on Request

Immigration Status: Permanent Resident (Green Card)

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