Design Engineer

DivyaKumar Kesharwani

****, ************ **. *****: 541-***-****

Apt. 524, Austin, TX, 78749 Email:*******@*****.***

Education:

Masters of Science (MS) Bachelor Of Technology (B.Tech)

Electrical Engineering Department Electrical Engineering Department

Oregon State University Indian Institute Of Technology, Madras (IITM), India

(Analog, RF and Mixed Signal VLSI Group) (Analog, RF and Mixed Signal VLSI)

GPA: 3.89/4 GPA: 8.2/10

Relevant Coursework:

VLSI Broad Band Communication Circuits, Analog Integrated Circuit Design, VLSI Data converters, Switch Capacitors Circuits

PLLs and Clock and Data recovery circuits, CMOS Integrated Circuits-II, Phase Locked Loops-II, Analog CMOS Integrated

Circuits, Delta-Sigma Data Converters, Device Modeling,

Digital Signal Processing Active Filter Design

Course Projects:

Design of audio delta-sigma A/D converter: A third order ΔΣ modulator for 2 bit ( 4 level) quantizer was modeled with OSR = 128 and

1.

OBG = 2. Later the non ideal effects, like mismatch in R/C, opamp non-idealities and DAC mismatch were analyzed. Entire ADC was

implemented using ideal components ( opamp, switches)

Design of inter stage gain amplifier for two-step ADC: Fully differential single stage amplifier with close loop gain of 4, settling error of 2.5e-

2.

4% and 5ns settling time was designed. Telescopic opamp with gain boosting technique was used to achieve the specs. Later, noise and

distortion analysis was done.

Design of integer N, Charge pump PLL: Integer N PLL with operating frequency of 0.25G – 1GHz and divider ration of 2, 4,8,16 was

3.

designed. For 1% jitter requirement and to save the power consumption, an adaptive loop bandwidth technique (with loop bandwidth

proportional to input frequency) was used.

*Various other similar class projects on PLL, opamp design, and switch cap filter design were done.

Research projects and Internships:

Oregon State University (Sept. ‘08 – April ‘10) under Dr. Patrick Chiang:

- Design of a track and hold architecture for sinusoidal sampling for high speed operation (GHz range).

Jitter in the sampling clock limits ENOB in high speed operating (time interleaved) ADCs. Employing sinusoidal clock with inherently less jitter

than conventional square wave (esp. at higher frequency) with specific phase alignment of clocks gives ENOB of 7-10 bits at 4GHz operation.

(Premise: It’s easy to generate high frequency sine wave with less jitter as compared to square wave). The chip was designed and fabricated in 90nm

CMOS process.

- On-die Adaptive Compensation for current leakage and mismatch in charge pump in PLLs.

Demonstrated using a Matlab behavioral model, an adaptive compensation loop to minimize the reference spurs caused by charge pump mismatch

and leakage current, by changing the charge pump current using a feedback control employing the sub-sampled DSP measurement of VCO output. A

publication on this work is accepted for ISCAS-IEEE ’09.

Cosmic Circuits Pvt. Ltd., India (June ‘07-Aug. ‘07)

- Analysis of mismatch in current sources transistors in current steering DACs.

The effect of segmentation in DAC DNL and INL performance and DNL Yield was studied. Using the Monte carol simulation, I derived a simple

Binomial Expectation formula for predicting the DAC DNL yield of fully unary implemented DAC architecture. The formula is being used as

company proprietary.

Indian Institute of Technology Madras, India (Final Yr. Project – ‘08) under Dr. Nagendra Krishnapura

- Testing of ZigBee (IEEE 802.15.4) protocol based transceiver chip.

Characterization of Charge pump PLL based Frequency Synthesizer designed for ZigBee protocol based transceiver. The testing involved the

functional verification of frequency synthesizer using various mixed signal chip testing equipments.

Publications:

A conference paper on “Measuring and Compensating for Process Mismatch-Induced, Reference Spurs in Phase-Locked Loops Using Sub-Sampled DSP” was

presented on International Symposium on Circuits and System-2009 IEEE (ISCAS-IEEE)-2009.

Accolades:

1. IIT-JEE:- Secured ALL-INDIA-RANK 327 in Joint Entrance Examination(JEE) 2004 conducted by Indian Institute of Technology, INDIA,

competing with 2,00,000 students.

2. KVPY:-Selected in the first round of Keshore Vaigyanic Protsahan yojayana conducted by Department of Science and Technology, Government of

INDIA.

3. Regional honor:-The local newspaper "DeshBandhu" awarded an accolade for best all round performance, academic and extracurricular activities.

4. Merit-cum-means scholarship (MCM):-Awarded MCM scholarship by Indian Institute of Technology Madras on the basis of merit and continuum

progress of student.

5. Placement: Kawasaki microelectronics and Cypress semiconductor offered associate design engineer job after undergraduation-2008.

Applications: Matlab, Cadence (Virtuoso, Specter), Eldo, Spice, Verilog-A.

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