Engineer Manager
Resume:
BENJAMIN S. LOUIE
Fremont, CA 94539
*******@*****.***
OBJECTIVE: Seeking a Technical Management or Technical Contribution
position which utilizes my technical expertise in IC
Design along with my communication, organizational and
planning skills.
SUMMARY:
. Over 16 years of experience as a Design Manager,
Technical Contributor and Project Lead
. Design Lead for Micron's first NAND FLASH Memory (2Gb).
Led project from concept to production in an aggressive
13 month schedule. Defined and developed: Chip
Architecture, Register Control Interface, State Machine
Architecture, High Voltage control and Path, Program and
Sense blocks, Column and Block Redundancy
. Experience designing every block within NAND and NOR
FLASH
. Expert at inventing, designing and implementing test
modes to improve yield and reduce test times/costs
. Innovative and proven problem solver with over 30 US
Patents Issued
EXPERIENCE:
Jan 2007 to Dec 2009 Design Manager
Micron Technology Inc., San Jose, CA
Researched feasibility of new architectures for NAND FLASH
including multi chip options and removing periphery blocks
like controller and analog. Provided competitor analysis
reports. Assisted and reviewed reverse engineering
reports. Led projects for the Logic/Controller block
functional group with the goal to provide all NAND designs
with a synthesizable controller block. Worked on
development, design and verification of new architectures
for new MLC devices beyond 3 bit per cell. Implemented and
verified test modes on new MLC 3+ bpc design.
June 2004 to 2006 Design Manager
Micron Technology Inc., San Jose, CA
Worked on developing new test modes for new 2 bit per cell
design. Aligned test mode features across all design
groups within Micron. Stepped in to provide technical and
managerial support of MLC project which was significantly
behind schedule. Set up and implemented an aggressive
verification plan to help push project back on schedule.
Managed verification teams in US, Japan and Italy. Created
a cross site verilog netlist release system. Managed
tapeout of 2 bit per cell MLC device. Supported debug,
production release and yield improvement of this chip.
Worked on developing a Verilog environment to allow
modeling for Analog behavior of MLC NAND.
June 2002 to 2004 Design Manager
Micron Technology Inc., San Jose, CA
Taped out array reduction of 2Gb device to 1Gb. Handled
debug, yield improvement, cost reduction, die
characterization and performance improvements for SLC
devices. Interfaced with Product, Test and Process
Engineering groups to apply feedback and develop new test
modes for new MLC (2 bit) designs.
June 2000 to 2002 Design Section Manager
Micron Technology Inc., San Jose, CA
Design Lead for Micron's first NAND FLASH memory design
(2GB). Lead a team of 10 Designers and 15 Layout Designers
from concept to production within 13 months. Interfaced
with Process Technology to provide required devices and
process specifications to meet design requirements. Worked
with Product and Test Engineering to provide test modes to
improve time to market. Defined and developed: Chip
Architecture, Register Control Interface, State Machine
Architecture, High Voltage control and Path, Program and
Sense blocks, Column and Block Redundancy. Researched
alternative memory technologies like MRAM, Phase Change and
other alternative charge storage devices.
June 1999 to 2000 SENIOR DESIGN ENGINEER
Micron Technology, San Jose, CA
Worked on low cost Mass Storage NOR devices and Flash
cards. Designed new NOR architecture to reduce cost by
moving blocks like pumps and controller off NOR FLASH chip
and onto Flash Card space. Designed and simulated negative
pumps, positive pumps, data path control circuits, column
and block redundancy. Ran full chip simulations using
hsim. Worked with Nassda to deal with hsim problems
related to FLASH memories and to develop a cell model for
NOR and NAND. Provided LVS/DRC debug support for layout
resources.
June 1998 to 1999 SENIOR DESIGN ENGINEER
Micron Quantum Devices, San Jose, CA
Design Lead for 16Mb Even Sector Boot Block Flash Memory
Design. Led team of 8 new college graduates to complete
project within 6 months. Provided full chip schematics,
floor planning, managed layout resources, debugged LVS/DRC,
and ran full chip verilog/hspice simulations.
June 1996 to 1998 INTEGRATED CIRCUITS DESIGN ENGINEER
Xilinx Corp, San Jose, CA
Worked on design and development of new FPGA products.
Provided simulations and designs for XC4000X family.
Provided HSPICE models and simulations of critical circuits
such as clock networks, oscillators, input delay, read-
back, and configuration logic. Created test patterns
using Xilinx's new M1 software. Developed methodology and
worked with Layout Design Engineers on LVS and DRC using
Dracula. Worked on die shrinks, die re-layouts and new
foundry tapeouts. Used Rubicad's layout compaction tool to
automate layout for process migration. Created and edited
schematics when necessary. Performed EM analysis of power
busses. Assisted during debug and bench testing of new
silicon.
June 1994 to 1996 PRODUCT/TEST ENGINEER
Xilinx Corp, San Jose, CA
Worked on development of new FPGA and Serial PROM (SPROM)
products. Utilized knowledge of Cadence Opus/Edge and
HSPICE to work with IC Design on design for testability,
memory mapping, bit generation. Debugged Xilinx's new Epic
FPGA software. Generated test and characterization
patterns and test methodology for new Xilinx XC4700 FPGA.
Developed method of automating test patterns using Perl
scripts. Debugged and analyzed new silicon. Developed
Test and Characterization Programs for Xilinx SPROM devices
using MegaTest GIIex Tester. Transferred and setup
offshore test at Taiwan Semiconductor Corporation (TSMC).
Provided failure analysis on SPROM devices. Qualified and
released 0.85?m EPLD SPROM and 0.6?m FLASH SPROM. Handled
initial SPROM production issues and training of sustaining
engineers and technicians.
SUPPLEMENTAL RESEARCH ENGINEER
Sept. 1993 to 1994 IBM Almaden Research Center, San Jose, CA
Provided research on IBM Lexmark Printers to improve
development processes. Designed and conducted laboratory
experiments. Interpreted results. Input data from
experiments into spreadsheets and word processors.
Researched theories in Electrophotography.
June 1993 to MANUFACTURING ENGINEER INTERN
Sept. 1993 Applied Materials, Santa Clara, CA
Analyzed and revised assembly procedures and part
specifications for the Etch Chamber of the Precision 5000.
Generated and implemented Engineering Change Orders.
Monitored assembly floor production. Handled assembly
floor problems and Discrepant Materials Reports.
EDUCATION: Santa Clara University, Santa Clara
Bachelor of Science in Electrical Engineering, June 1994
Magna Cum Laude Honors
Honors and Awards: President of Tau Beta Pi (Engineering
Honor Society), Dean's List Award Recipient in 1990, 1991,
1992, and 1993, National Dean's List 1991 and 1992.
Santa Clara University, Santa Clara
Masters of Science in Electrical Engineering, June 1998
Other Training: Kepner Tregoe Problem Solving and Decision
Making
RELAVENT SKILLS: Cadence Virtuoso, Hsim, Hspice, VerilogXL,
NCVerilog, Design Compiler, Design Sync, Perl, C Shell,
Cadence DIVA, Microsoft Excel, Microsoft Word, Microsoft
Powerpoint, Microsoft Project, Microsoft Visio
PATENTS:
. U.S. Patent #7707467, Input/Output Compression and pin
reduction in an Integrated Circuit, issued April 2010
. U.S. Patent #7546400, Non-volatile memory devices and
control and operation thereof, issued July 2009
. U.S. Patent #7369447 and #7123521, Random Cache Read,
issued May 2008 and October 2006
. U.S. Patent #7345924, #7269066 and #7505323, Programming
Memory Devices, issued March 2008, Sept 2007 and March 2009
. U.S. Patent #7336537 and #7336536, Handling Defective
Memory Blocks of NAND Memory Devices, issued February 2008
. U.S. Patent #7274607 and #7532524, Bitline Exclusion in
Verification Operation, issued Sept 2007 and May 2009
. U.S. Patent #7254049 and 7486530, Method of Comparison
between Cache and Data Register for Non-Volatile Memory,
issued August 2007 and Feb 2009
. U.S. Patent #7239552 and #7532517, Non-Volatile One Time
Programmable Memory, issued July 2007 and May 2009
. U.S. Patent # 7447847 Memory Device Trims issued Nov 2008
. U.S. Patent #7213188, Accessing Test Modes Using Command
Sequences, issued May 2007
. U.S. Patent #7196930 and #7630236, Flash Memory Programming
to Reduce Program Disturb, issued March 2007 and Dec 2009
. U.S. Patent #7159141 and #7539896, Repairable Block
Redundancy Scheme, issued January 2007 and May 2009
. U.S. Patent #7154782, #7154782,0 #7154780 and #1723512,
Contiguous Block Addressing Scheme, issued December 2006
and Oct 2006
. U.S. Patent #7120068 and 7505357, Column/Row Redundancy
Architecture using Latches Programmed from a Look Up Table,
issued October 2006 and March 2009
. U.S. Patent #6370070, Methods for Alternate Bitline Stress
Testing, issued October 2006
. U.S. Patent #6304504, Methods and Systems for Alternate
Biltline Stress Testing, issued October 2001
. U.S. Patent #6262920, Program Latch With Charge Sharing
Immunity, issued July 2001
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