Engineer Design
Resume:
MURALI KRISHNA GUDIMELLA
Fremont, CA
E-mail: ********@*****.**.**
USA Phone: 1-510-***-**** (Mob)
CAREER OBJECTIVE:
Seeking opportunity to prove my skills in Silicon with the role as
Analog/Mixed-Signal, RF Layout/Mask Design Engineer.
SUMMARY/SPECIAL SKILLS:
IC Layout/Mask Design, with 9+ years of experience in Analog, Mixed-signal,
RF and I/O. Duties include chip lead, block lead, I/O cell layout from
schematic, project library creation, ownership. I am experienced with all
verification flows, including DRC, LVS, ERC, ESD/Latchup, ANT, RVE, QRC,
density, EM, IR and some skill programming. Experienced with Cadence
Virtuoso LE, Virtuoso XL, schematic composer, ADE, SPECTRE, Mentor graphics
ELDO, Hercules, Dracula, Diva, Assura, Calibre, VAVO/VAEO and Cliosoft SOS.
Experienced with .35, .25, .18, .13, 90nm, 65nm and 40nm CMOS processes and
also experienced in both BiCMOS and BiPOLAR process. I have experience in
PCELL creations and familiar in running extractions with
Calibre/Assura/Dracula and also familiar in debugging/modifying extraction
rule decks. Currently working with Cadence 6.1 version.
JOB EXPERIENCE DETAILS:
Ikanos Communication Inc., Fremont CA April'07 to till
date
Sr. Staff Engineer, Layout/Mask Design
Duties include; doing layout design from scratch cell level to full chip
level including I/O cell layouts. I am also involved in power planning,
chip floor planning with I/O pin placements, complete verification and
tapeout of full chip. Additional duties include; running VAVO/VAEO for
blocks ADC, DAC, Line drivers, and modification of rule decks to catch
extra verification checks like deep-nwell device models. Recently taped out
BiCMOS chip includes Line driver and LNA blocks which is running with 0.35u
JAZZ BiCMOS process for VDSL2 applications. I have experience in layout
design for Receiver block, DAC and Reference block for SERDES chip with
charted 65nm process. I have also worked on doing block level layout to
full chip tapeout including I/O cells of Hybrid Line driver chip with 0.5u
Philips bipolar process. I have also involved in doing layout design for
ADC, VCXODAC, Filters, Full chip integration, verification and tapeout with
0.25u TSMC CMOS process. I work closely as the main contact with key
personnel at several FAB's including TSMC, PHILIPS, charted and JAZZ. I
also involved in creating layout design for ESD diodes for Custom I/O pads
and in Power-cut regions.
Currently working on TSMC40nm Project for G.HN product, involved in doing
layout design for ADC, Regulators and reference block.
Ikanos Communication [India] Pvt Ltd., Bangalore India Mar'05 to
April'07
Analog Layout Engineer
I have been involved technically in all projects including floor planning,
block layouts, full chip layout, I/O cell layouts, verification and
tapeout. I was responsible in doing layout designs for 65n, 90n, 130n TSMC
PLL; 0.25u 14-bit VCXODAC with TMSC process and 0.5u 20- dBM Line driver
chip with NXP process.
United Microelectronic Solutions Ltd., Bangalore India Dec'01
to Feb'05
Sr. Design Engineer
I have involved in doing layout designs for 0.13u PLL with TSMC process for
a Digital chip.
I was worked on modifying TSMC I/O cell layouts for meeting custom design
requirements.
I have contributed in layout designs for PGA, LNA, Tuner circuits and Full
chip verification for CPE chip which was run with 0.25u TSMC process. I was
familiar with RF layout design such as 2.4G LNA, Gilbert's Mixer with TSMC
process and 2.4G Si-Ge BICMOS LNA with 0.8u AMS process for Wireless LAN
applications. I was also involved in making layout design blocks such as
36MHZ PLL, Low Voltage Gm-C filters (3rd and 5th Order), 6-Bit 66MSPS
single step Flash ADC with TSMC process and all the blocks were designed
for wireless LAN applications. I have worked on block level layout designs
such as 20MHz-205MHz 5-band PLL and 10-Bit current steering DAC for VIDEO
application chip. I have also worked on custom circuit designs for digital
blocks and current steering 10-Bit 76MSPS DAC.
INTEL Bangalore India (Contractor) Apr'03 to
Oct'03
I was also involved in doing RF layout design for Transmitter blocks, MDLL,
Programmable divider, Pre-scalar divider and full chip verification for an
UWB Transceiver chip which was run with 0.13u INTEL RF process. I was
worked on implementing Inductors and Transformers, with INTEL R&D group.
V-design Private Limited Pondicherry India Feb'01
to Nov'01
Tr. Design Engineer
. Microprocessor Project: This project was implementation of 4-Bit
Microprocessor. It contains the hardware RAM, ROM, Multiplexers,
Program counter, Instruction decoder, ALU, Tri-state buffer and Timing
control. Each and every block was coded in VHDL.
. Digital Alarm Clock and Frequency Synthesizer: This project contains
the hardware Keyscan, Keybuffer, Shifter, Frequency divider; display
as common blocks. Alarm control, Soundblock, Digital alarm clock
blocks for Digital Alarm Clock and Divisor value, Count Value,
Frequency synthesizer blocks for Frequency Synthesizer.
Bachelor of Engineering PROJECT: (Academic)
. TITLE: MICROPROCESSOR BASED PROGRAMMABLE POWER SUPPLY.
. HARDWARE: Microprocessor interfaced with PPy.
. SOFTWARE: Assembly language (8085).
. SUMMARY:
* Interfacing a Microprocessor (8085) to a power supply, PPI (8155),
Memory EPROM
(2764) keyboard and display.
* Programming 8085 for Dual display, one for entry and other for
output display.
* Solid state switching of voltages and Variable voltage 0-30 Volts.
EDUCATIONAL QUALIFICATION:
Bachelor of engineering in Electronics & Communications with first Class
from Bapuji
Institute of Engineering and Technology- Davangere India passed out in
Oct'2000.
RECOGNITION AWARDS:
Achieved Two times IKANOS RECOGNITION AWARD for successfully Taping out the
CHIPS in short duration and Third Award for executing and meeting deadlines
for the HLD_CO6J project and reducing the die size by 30% to result in cost
savings.
WORK AUTHORISATION:
Eligible to work in USA. Hold active H1B VISA.
REFERENCES: Available upon requested.
Contact this candidate