SHAMBHAVI KULKARNI

****Brookline Ave,Apt #** Phone: 513-***-****

Cincinnati, OH 45220 Email: ablcul@r.postjobfree.com

Electrical engineer with Masters in VLSI and Embedded Systems having 2 years of experience in design,

implementation, verification, testing and validation of the chips using different CAD tools.

SUMMARY

Experience in design and verification of chips using behavioral and RTL models in VHDL and Verilog.

Extensive experience in design and development of software components using Object oriented concepts.

Designed and tested North East router chip right from the specifications. It is a custom bitslice design. Drew the

layout using magic layout editor and performed the transistor level simulations using Hspice & Irsim. Tested the

same chip for fault-patterns using HP 165000A Logic Analyzer.

Experience in design and implementation in Xilinx ISE and Quartus II and testing on FPGA boards.

Strong, proven communication skills and interpersonal skills with experience in team management,

client communication, requirement gathering and customer support

TECHNICAL SKILLS

Assembly languages: 8085/86, Microcontroller 8051, ARM

Programming Skills: VHDL, Verilog, Embedded C, C, C++(STL),COBOL, Perl

SQL server 2005

Database:

Development Tools: MATLAB, Dev C++, Quartus II (9.1 Version),Xilinx ISE 11.4

Magic, IRSIM, HSPICE, OrCAD, ModelSim 6.5d,Cadence,Virtuoso,Scirroco

CAD Tools:

Platforms: Windows, Linux, Sun Solaris, Unix

PROFESSIONAL EXPERIENCE

Aug08-Present

University of Cincinnati

Member of Research Group (Digital Design Environment Lab)

Capstone Project: Implementation of IEEE-1149.1 Standard

• Completed FPGA implementation of IEEE-1149.1 standard incorporated at chip level in Xilinx ISE 11.4 and

ModelSim 6.5d.

Verified the Functionality of schematic on Digilent’s Basys board with Xilinx Spartan 3E FPGA.

Completed implementation of boundary scan architecture for portable automatic testing equipment for

digital circuits in Magic which includes full custom layout of the chip.

VLSI Project: North East Route Checker

Planned and designed bit slice and replicated to create an array in Magic and simulated using IRSIM and

HSPICE.

Completed Padframe connections of 40 pin Chip with implementation of testing strategies.

Completed Behavioral and structural modeling of whole design in VHDL.

Embedded Systems Project:

Designed 8 bit simple embedded processor.

Planned detailed architecture, interfacing of different modules, bus sharing and Instruction set.

Implemented using Verilog on Altera’s Quartus II (9.1 Version software).

Completed testing of separate modules on Altera’s UP3 board which makes use of Cyclone Chip.

VLSI Design Automation Project:

Implemented Simulated Annealing algorithm to solve balanced bi-partitioning problem using C++.

Completed testing of the program over ten benchmarks involving 1,00,000 cells and 1,20,000 nets.

Compared results i.e. Cutset, Fitness, CPU time with results of Kernighan-Lin algorithm.

Low-Power VLSI Circuit Design Project:

Designed Full adder Circuit (Static CMOS and Domino Implementation) in Magic.

Analyzed power dissipation of both implementations by checking short circuit, leakage and dynamic power in

Hspice.

VLSI Test and Validation Project:

Planned strategies to test chip using HP Logic Analyzer.

Implemented Full scan chain testing, Functional testing, Stuck at Faults testing,Stand alone component testing

with the help of Pattern generator in HP analyzer .

Syntel LTD Nov 07 - Jul 08

Graduate Engineer Trainee

Completed training on COBOL, Mainframes platform and C++.

Worked with a team of six on credit card processing containing execution and testing of different online

transactions in Banking and Finance domain.

ACADEMIC QUALIFICATIONS

M.Eng. in Electrical Engineering (VLSI and Embedded Systems ) -University of Cincinnati, Ohio GPA: 3.3/4

Relevant Coursework: Physical VLSI Design, Low Power VLSI Circuit Design, VLSI Design Automation,

Embedded Systems, VLSI Test and Validation, Management of Professionals, Fundamentals of leadership,

Optimization models for managers, Effectiveness in technical organizations .

GPA:

B.E. in Electronics Engineering –KIT’s College of Engineering, Kolhapur 3.9/4

EXTRACURRICULAR ACHIEVEMENTS

• Participant, System on Chip Design Using VHDL & FPGA seminar, Ramaiah School of Advanced Studies, India.

Recipient, Second Prize at National Level Paper Presentation Competition,KIT’s College of Engineering,

Kolhapur, September 2006

Title of the paper: MEMS Technology

Member, IEEE, Kolhapur, Maharashtra, India, Jun 2004- Jun 2007.

Member, Indian Society for Technical Education, Kolhapur, Jun 2004-Jun2007.

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