Engineer Electrical
Resume:
Email: ***********@*******.***
Cell Phone: 408-***-****
Minhtam Pham
San Jose, CA 95122
OBJECTIVE: Seeking a Electrical Engineer position.
EDUCATION: Santa Clara University.
B.S.E.E Graduate March 1997.
EXPERIENCE:
. Sept 2011 to Nov 2012: Senior Product Engineer, Volterra Corp. Fremont,
CA
. Product engineering for high current, fast switching & fast response CSP
flip chip buck regulator for server and note book. Support products from
preliminary spec to mass production and finalize Data Sheet Electrical
Table parameters according to characterize data from all corners, across
temperatures and voltages with +\- 4 sigma & Cpk limits. Perform
reliability Htol, ESD/LU/CDM, Emmi, x-ray, fibbing, etc. to support
design. TPM for POL (Citron/Absolut point of load), Slave/Master
(Controller/ PT slaves) & Integration of Controller/Slave products. Data
Power efficiency.
. 2008 to Sept 2011: Sr. Product/Characterization Engineer, iML Corp.
Campbell, CA
. Characterize, write test plans, improve yield, working with designer to
debug issues, and fully support LCD Products (LDO, Buck, Boost, inverting
Buck-Boost, CP, PGAMMA, PVCOM, VCOM, DVR, Level Shifter, single channel
and multiple-channels integration products). Knowledge of device physic,
process, design and device layout concepts. Support products from
preliminary spec to mass production and finalize Data Sheet Electrical
Table parameters according to characterize data from all corners, across
temperatures and voltages with +\- 4 sigma & Cpk limits. Perform
reliability Htol, ESD/LU/CDM, Emmi, x-ray, fibbing, micro-probing, etc. to
support design.
. Help designer to review and improve design and data sheet. Work with
Marketing, Designer, Layout, TE, QA and Operation engineers to define
product definition in order meet customer specification and deliver
defective free device to customer in a timely manner. Understanding Op-
amp concept of 3-dB gain, phase margin, poles, zeros, R & C compensation
and PMIC PWM basic design concepts.
* 2000 to 2008: Sr. Product/Characterization Engineer, IDT/(ICS), San
Jose, CA.
1. Expert on bench test, application and Characterization of Clock chips
(frequency timing chip) consisting of many PLLs (phase lock loop) for PC
clock. Held functional review meeting to bring up all the functional and
performance issues that are out of spec and held training session to
familiarize everyone with new features and requirements. Work on RMA, low
yield analysis, release package for full char, decap, fibbing and micro
probing of non functional parts and new bases. Support product from
beginning of tape out to release of product by working closely with
designers, marketing, and manufacturing and in charge of many bases to
reduce low yield and RMA (customer return parts for analysis).
1. Expertise with these equipments: Agilent infiniium 4 GHz oscilloscope,
Agilent 1Hz to 26.5 GHz Spectrum Analyzer, Curve tracer, Tektronix scope,
Lab view, Math LAB, Automation Tester, Pulse/Pattern generator, MDA
(Modulation Domain Analyzer), Frequency counter (use for freq accuracy
which is reported error in ppm) and many more lab equipments.
1. Expert on functionality, performance check, application and debugging:
Frequency accuracy, Spread tracking, phase noise, Long record length data,
I-V curve, SE and differential cycle to cycle jitter using M1 and 4GHz
infiniium scope, SE and differential skew, X-over, slew rate, accumulate
jitter, amplitude modulation, PLL not locking, Power up time, power ramp
rate sensitivity, Power supply noise rejection ratio (PSRR), output disable
time, output on and stabilization time, Crystal frequency error, Input
thresholds, Input sensitivity (Duty cycle and noise start up), Spread
spectrum percentage and modulation rate, Loop filter Bandwidth.
Recognizing and debugging shifted edges, PLLs not locking or not tracking
each other, missing pulses, accumulate jitter, spread spike, smbus
problems, signals coupling, across VDDs and temperatures sensitivity, Full
Crystal Characterization.
* 2/1997 to 6/2000: VLSI Design Engineer, LDIC, San Jose, CA.
. Designed, modified, simulated, and tested high frequency
Universal
READ/WRITE pre-amplifier with Servo Write Capability for 4 up to
8 channels.
. Modified and simulated DAC, WRITER, VDDFLT, Positive Reset Pulse
(PLR), MODE, Voltage Reference (VREF), Read Unsafe (RUS), Write Unsafe
(WUS), Head Voltage Monitor (HVM), Digital Head Select (HS), Serial Port
(SP), RBOOST, Analog and Digital Buffer head voltage (LPCROWB), and
Temperature Asperity Detection (TAD) blocks.
. Assisted on developing chip specification.
. Created layouts for the most complex and sensitive block (the
Read / Write) block.
. Did floor planning and laying out the TOP for the Whole Full
Custom Chip using Cadence Virtuoso, and Compass Layout CAD tools.
. Ran Design Rule Check (DRC) and Chip Verification (LVS) for the
Whole Full Custom Chip using Dracula.
. Laying out PCB board using PADs software and power logic 3.0.
Interact with our Fab Partners Sanyo and Rohm.
. Work on Avanti Appolo and Cadence Silicon Assembler Place and
Route tools.
. Designed, setups, debugged, tested and troubleshoot for Magneto-
Resistive (MR) HeadPCB.
* 2/1996 to 11/1996: Technician/Test Engineer, Trazar Corporation, San
Jose, CA.
. Board level design and testing, testing AMU (automatic matching
network) and write program in forth for microprocessor.
. Built and test a Chuck Pulser (an equipment to be used in a wafer
machine).
. Built, troubleshoot, and tested PCB.
. Designed and built a microprocessor based traffic light
controller.
SPECIAL SKILLS :
* Design: Knowledge of BiCMOS & CMOS mixed-signal IC design, voltage
reference, op amp,
comparator, differential pairs, DAC, ADC, D, J-K flip flops,
current sources, oscillator,
Noise and cross talk problems, low power consumption, DC offset affect,
PSRR, PLL,
Channel Separation, Thermal Asperity, of high-speed analog IC
Design and speeds over
450 MHz using 0.8 um effective length technology Bipolar and
BiCMOS process.
. Knowledge of microprocessor, EEPROM, ADDER, COUNTER, CPU.
. Understand every aspects of Physical design flow such as chip
floor planning, place & route,
optimization and compaction, extraction, full chip timing,
physical verification, and cell library
evaluation.
* CAD Tools : Cadence virtuoso and composer, Compass layout and logic
assistance, Tanner layout, Power Logic 3.0, PCB Pad layout, Power View
Logic View, Visio 4.1, Sun Solaris Station, Mental Graphic, Generic Cad,
Avanti Apolo, Cadence Silicon Assembler Place & Route tools.
* Electronic Equipment : 4 GHz Spectrum and Network Analyzer, 4 GHz
Oscilloscope,
Differential and Current Probe, Function Generator, Transistor Curve
Tracer, Voltage meter,
Thermometer, Diagnostic, SMT soldering.
* Software : HSPICE, SPICE, Star_Sim, UNIX, C, Forth, Assembly, Excel,
Words, DOS, Math Lab, Lab View, Pascal, FORTRAN, Windows Xp, 95, 98, NT,
Office 2000, Microsoft Office 95, 97.
RELATED CLASSES :
* MIXED SIGNAL IC DESIGN
* ANALOG and DIGITAL IC DESIGN
* ADVANCED IC DESIGN
STATUS: U.S. Citizen.
Contact this candidate