Engineer Electrical

Aparna Rampal

***** ********* ******, **********, **. 91311,

Phone: 206-***-****, ***********@*****.***

OBJECTIVE

To gain a dynamic and challenging role in the Electronics, Computer,

Hardware, Electrical and Communication Industries that will offer me

opportunities to put my education, experience and skills to work towards

technical research and analysis, operations, manufacturing and

development/improvement of associated processes while at the same time

providing me long-term career growth possibilities.

CORE COMPETENCIES

System Design and Test, Digital Electronics Design and Test, Verification

and Validation, Technical Operations and Support, Manufacturing and

Industrial Engineering, Research & Analysis, Hardware Implementation and

Troubleshooting, Technical Writing/Documentation Engineering.

TECHNICAL PROFICIENCIES

Numerical Computing: MATLAB, MS Excel

Requirements Management: Telelogic DOORS

Configuration Management: ProSoft XStream, Razor, JIRA

Digital Design & EDA Tools: Cadence, Virtuoso, Encounter ORCAD, Xilinx ISE

Hardware Descriptive Languages: Verilog

Software Languages: C++

Software Packages: MS office including Microsoft Project and

Microsoft Visio

Operating Systems: UNIX, Linux, Windows 98x/NT/2000/XP/Vista

Equipment: Tektronix Logic Analyzer, CRO, Function Generator,

RF Generators, Programmable Power Supply,

VSWR meter

PROFESSIONAL EXPERIENCE

Sledgehammer Corporation, India Commercial and

Residential Construction

Electronics /Electrical Engineer

01/2010-To Date

o Key design consultant for all commercial and residential projects.

o Responsible for design, development, installation, test and

maintenance of Smart Security alarm systems in residential and

commercial properties

o Knowledge and usage of building and electrical codes. Developed spec

sheets and building plans

o Developed and tested smart module designed for automated evacuations

from elevator systems during power outages.

Sensis Corporation, Syracuse, NY Air Traffic

Surveillance Systems

Engineer - System Life Cycle/Electronics

08/2007-08/2008

o Developed Standard Operating Procedures and Work Instructions

o Created deliverables including Interface Control Documents, Analysis

Reports, Technical Presentations, Whitepapers, Operation Manuals

o Conducted Technical Interchange Meetings, Requirements, Design,

Performance and Acceptance Reviews

o Performed Requirements Definition and created Statements of Work using

DOORS

o Participated in all Product Development phases encompassing all stages

from Requirements Engineering to System Maintenance

o Performed Data research, analysis, documentation and communication

o Created test procedures .Responsible for factory Acceptance Testing

and Troubleshooting

o System Deployment and Optimization. Responsible for maintenance of

internal Wiki.

o Knowledge of OSHA, NEMA, FAA, MIL, UL, IEEE and other standards

Portland State University, Portland, OR M.S.

Electrical and Computer Engg.

Teaching Assistant - Electrical and Computer Engineering

01/2006-01/2007

o Conducted and Supervised lab sessions dealing with:

o Design, timing analysis, implementation and verification of

synchronous state machines using both discrete and programmable

logic devices.

o Design, Verification and Analysis of asynchronous state

machines, arithmetic circuits and devices, microprocessors,

o Design and interfacing of combinational and sequential circuits,

memory systems and FSMs

o FPGA and ASIC prototyping, programming and verification

o RTL, DTL, TTL, ECL logic implementation

Radius Power Inc., Mohali, Punjab, India

Manufacturing/Industry

Electronics Engineer 07/2004-

11/2004

o Responsible for quality control of electronic and electrical filters

transformers and power supplies and supervised their assembly

o Developed test systems. Wrote test procedures for testing high

performance electronics products.

o Researched and developed test methods of new products by working with

design engineers

o Interfaced with product managers and provided full system support

during new product introduction phase.

Reliance Infocomm. Pvt. Ltd., India

Communications

Electronics Engineer 06/2003-

01/2004

o Worked with the CDMA Cellular Service Provider on project dealing with

set up of additional BTS (Base Transceiver Station) sites to increase

network coverage

o Responsible for Site Surveys, Installation/Commission & Testing for

Reliance Infocomm CDMA network sites

o Switching OA&M.

o Created a report on "CDMA in the Telecom Industry" which dealt with

aspects like scope, advantages, infrastructure, maintenance and up-

gradation related to cellular technology (submitted to Ministry of

Communications and Information Technology)

RELEVANT EXPERIENCE: Other Projects undertaken

Microprocessor Architecture: Verilog project modeled a high speed, 2 way

set associative, L1 cache controller with interface to memory (4GB DRAM)

and the microprocessor. Non-allocate write miss policy and LRU as the

replacement policy were applied.

Computer Architecture: C project modeled the PDP-8 simulator which

supported MRI, Group 1 and Group 2 instructions and the end result of an

execution was the a display of the instruction type, number of clock

cycles, instruction count, total number of clock cycles consumed, CPI for

the executed program as well as the contents of the AC and L registers.

Hardware Description Languages

o Cyclic Redundancy Check Codes: Generated coding systems of 1, 8, 16

and 32 input bits for the generating polynomial CRC16Q using the

pdcodes package. Collected data on throughput in Mbps and resources

used in gate equivalents for the various cases of the CRC 16

polynomial used in data analysis.

o Variable Length Coding: Implemented and optimized the Variable Length

Encoder (MPEG Systems). Used the whole model method of high level to

low level verification to implement and improve the VLC and its

constituent blocks on Xilinx devices. Investigated alternatives and

improvements, which were implemented by switching to Block RAM.

o Data Encryption Standard: Implemented and optimized the fast operation

and small size DES. Timing improvements were made by use of design

constraints, which were applied through the Xilinx GUI. Place and

Route tools and Static Timing Analyzer were used to constrain paths

and placements and get timing information related to the same

respectively.

Digital Integrated Circuits

o Designed spec based circuits (static CMOS inverter, 3 I/P AND/OR Inver

and 3 bit fill adder) in Cadence design environment on TSMC NFET and

PFET models.

o Performed DC and transient analysis on each and employed Spectre-S for

simulations and Virtuoso for cell layouts.

o Prepared schematics for diode load, CMOS and multiplexer inverters

using the cadence composer tool and after simulation analyzed their DC

and transient characteristics.

Ethics of Development in a Global Environment

o Addressed the issue of "Bridging the Digital Divide" which dealt with

public programs, Corporate Social Responsibility initiatives and NGO

efforts to eradicate information poverty caused due to lack of digital

and information technology resources in the developing world.

o Performed Case Study on "Brazil and the Ethanol Industry" to address

issues related to fuel shortage, rising fuel prices and pollution and

to investigate alternatives for the same.

Masters Final Project

o Implemented "Microprocessor based Home Automation System" which was a

Microcontroller (89C51) based, telephone triggered device controller.

EDUCATION & CERTIFICATIONS

o M.S. Engineering Technology Management, Fall 2008 - To Date (Part

Time) - Portland State University, OR

o M.S. Electrical and Computer Engineering, 2007 - Portland State

University, OR

o B.S. Electronics and Communications Engineering, 2004 - PTU, India

RESEARCH PAPERS

o Study of the limited capabilities of the North-bridge with reference

to the types and number of RAM and the incapacity of the same to the

types of South-bridges. An alternative to reduce limitations was

proposed.

o Simultaneous Subordinate Microthreading, its mechanics, hardware

support requirements, pipelining and its comparison with other

techniques that exploit instruction level parallelism.

o Linear Programming approach for sizing, Vth and Vdd in order to reduce

circuit power.

o Reliability Improvement for chips fabricated using deep sub micron

technology and layout based methods to improve reliability.

** References available upon request

Contact this candidate