Design Project

AK ***, ECE Dept. WPI,

ChenDate: February, ****

Shen Worcester, MA 01609

Graduation 508-***-****

GPA: 3.80/4.00 (Graduate Study) *********@***.***.***

PROFILE

• Well trained in design with C, MATLAB/SIMULINK, Verilog HDL and VHDL.

• Hands-on experience in FPGA/ASIC tools: Modelsim, Xilinx ISE, Altera Quartus II and Protel DXP.

• In-depth knowledge at ASIC design flow: RTL, verification, synthesis, static timing analysis and test.

• Knowledge at Embedded System design, RF Circuit, PCB, Linux, Microsoft Office, Latex.

• Proven team player and self-motivated in multitask environment with stress and pressure.

EXPERIENCE

Project Instructor Embedded Computing Lab, ECE Dept., WPI, MA 2009-2010

Innovate North-America Altera Design Contest 2009

• Led WPI’s group combined with other undergraduate students from ECE department in the contest.

• Offered instructions and suggestions on algorithm analysis and implementation.

• Set timeline for project progress and held meeting weekly.

• Analyzed hardware implementation errors and modified hardware structure in Altera DSP Builder and

Xilinx System Generator.

Teaching Assistant ECE Dept., Worcester Polytechnic Institute, MA 2008-2009

• Focused on lab instruction, project design and demonstration in 4 ECE graduate level courses.

• Cooperated with other graders in quiz grading; reported final results to course instructor.

• Gained experiences in achieving time-sensitive target with team cooperation.

• FPGA projects finished include: RS232 communication, VGA driver, SRAM driver, etc.

Master Thesis Embedded Computing Lab, ECE Dept., WPI, MA 2008-2009

Title: Design and Implementation of an Improved Soft-output MIMO Detector

• Developed the MIMO sphere decoding algorithm with a Rayleigh fading channel model in MATLAB.

• Researched the Sphere Detection Algorithm and principles of soft in soft-output decoder

• Proposed an optimized algorithm with improved BER performance and lower complexity.

• Simulated and implemented the decoder with the highest data throughput in XilinxVirtex-5 with

Xilinx ISE. (3.7Gbps/230MHz, 220,000 LUTs)

• Obtained experience in trouble shooting and ability of systematic design flow for hardware prototype.

Course Project Embedded Computing Lab, ECE Dept., WPI, MA 2008

Interfacing Embedded Processor with Customized IP Cores in FPGA (Report Available)

• Implemented an Embedded Processor using PowerPC core into Xilinx Virtex-4 FPGA.

• Implemented a customized IP core which is able to execute both extraction and multiplication operation.

• Evaluated the result by calling the IP core through the C program run in the PowerPC.

• Gained the experiences in embedded System design.

Directed Research Embedded Computing Lab, ECE Dept., WPI, MA 2008

The Implementation of FDTD Method in Solving Partial Differential Equation (Report Available)

• Evaluated the effect of floating-point operation in FPGA design.

• Built high-order finite difference time domain (FDTD) solution model for partial differential equation.

• Implement the model in Simulink and transferred it into HDL code through Xilinx System Generator.

• Analyzed the method of hardware/software co-design.

Course Project EST Dept., Huazhong Univ. of Sci. and Tech., China 2007

FIR Filter Design and Implementation

• Designed 8-tap 8-bit FIR filter

• Built the mathematic model in MATLAB and gained the tap coefficients.

• Designed the behavioral model with simulation in Modelsim and synthesized the design in Leonardo.

• Gained experiences in digital IC design and implementation.

Course Project EST Dept., Huazhong Univ. of Sci. and Tech., China 2005

3D Jet Engine Model

• Built 3D jet engine model for demonstration.

• Explored the OpenGL and C++ program language with Borland C++ Tools.

• Gained experiences in Computer Graphics and Windows API Function.

EDUCATION

Master in Electrical and Computer Engineering GPA: 3.80/4.00 2007-2009

Department of Electrical and Computer Engineering, Worcester Polytechnic Institute, MA

Bachelor in Electrical Engineering GPA: 83/100-****-****

Department of Electronic Science and Technology, Huazhong University of Science and Technology, China

RELEVANT COURSES

Analysis of Prob. Signals and Systems (A) Digital Signal Processing (A)

Fundamentals of RF and MW Engineering (B) Linear System Design (A)

Reconfigurable Computing Using FPGAs (A) Arithmetic Circuit (A)

Computer Architecture (A)

PUBLICATION

Kai Zhang, Xinming Huang and Chen Shen, "Soft Decoder Architecture of LT Codes" Signal Processing

Systems, 2008. SiPS 2008. IEEE Workshop on, pp.210-215, Oct. 2008

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