Engineer Design

Jaymin Patel

***** ****** ***** **. *** G***

San Diego Ca, 92130

Home Phone: 858-***-****

Cellular Phone: 760-***-****

Email: ************@*****.***

U.S. Citizen

Profile

RF/Analog IC Design Engineer with an M.S.E.E. and close to three

years experience in design of key RF and Analog blocks, post

silicon validation and debug of ICs, as well as experience in

working on qualification boards. Very passionate about

furthering my knowledge in engineering.

Professional Experience

September 2006 to March 2009 NextWave Wireless San Diego, CA

RF Analog Design Engineer

. 65nm CMOS Process Designs

o Validated baseband analog receiver as part of a WiMax

RF/Analog Chip through extensive simulations and design

adjustments. Receiver designed with 1.2V supply and consisted

of 3 pole Butterworth filter (biquad followed by RC Filter)

and driver stage. Baseband block designed with multiple gain

and bandwidth settings to filter desired RF channel

bandwidths.

o Designed PFD/CP circuit as part of a WiMax Integer-N PLL with

a 1.2V supply. Standard up/down tristate PDF/CP designed to

have phase noise less than -230dBA/rootHz at >100 KHz offsets

and phase mismatch delay less than 300ps.

o Designed low noise bandgap and 1.2V output voltage regulator

circuit with max spot noise of 40nV/rootHz at 100 KHz and

above. Bandgap and regulator designed to function over supply

of 2.35V to 3.3V and with digital signal level of 1.2V.

. 0.18um SiGe Bi-CMOS Process Designs

o Designed Bias Current Mirrors (PMirrors) for WiMax

transceiver chip. PMirrors designed to be central biasing

scheme for every circuit on RF/Analog Chip. Architecture

based on farming out proper bias from main bias generator.

o Designed Analog TestBus for signals <10MHz for WiMax

transceiver chip which allowed for debug of internal circuits

and nodes possible for Rx/Tx section of the RF/Analog Chip.

o Design and debug for multi-site Highly Accelerated Stress

Test (HAST) and High Temperature Operational Life (HTOL)

qualification boards for the RF/Analog chip. Worked with Ops

team to root cause issues and bring to completion

qualification testing. Tracked status and performed failure

analysis during qualifications. Chips in production.

o Temperature and voltage testing for RF/Analog Chip over

temperature and battery voltage range. Tested critical RF

parameters including Rx/Tx EVM, IP1dB, Gain, OIP3, and ACPR.

. Tested and debugged several RF/Analog circuits in lab including low

transmitter output power on HTOL boards due to bad matching network

and layout and low regulator output voltage due to bad routing in

layout.

June 2003 to June 2004 Broadcom Corporation

Irvine, CA

Engineering Intern

. Provided design support and assisted in simulations.

. Compiled UNIX programs to test various integrated circuits with

Teradyne Tiger and Catalyst System on a Chip Test Systems.

. Performed characterization, quality testing, and HTOL testing.

. Used Thermostream to test devices at broad range of temperatures.

. Verified HTOL and Layer bonding diagrams.

. Interfaced between Design Engineers and Test Engineer, and

Packaging Engineers.

. Performed yield analysis and microchip substrate failure analysis.

Education

Masters of Science, Electrical Engineering

Graduated May 2006

University of Southern California

Relevant Courses: CMOS Analog IC Design, RF Communication IC

Design, Array Antenna Design, RF Analog Filter Design, RF

Systems and Hardware, VLSI Design, MMIC Analysis and Design,

Mixed Signal IC Design.

Bachelor of Science, Computer Engineering

Graduated June 2004

University of California Irvine

Graduate Design Project

. 0.25um CMOS Process Designs

o Wideband TIA with gain of 1000 ohms and bandwidth of 2.5GHz.

o 1.8 GHz LNA achieved gain greater than 19dB and noise figure

less than 2dB across band.

o PLL with locking range from 1.75 GHz to 1.83GHz.

o 1.8GHz VCO with tuning range of 1.7GHz to 1.95GHz and phase

noise less than -125dBc/Hz at ?f=600KHz.

o LNA Mixer (Current sharing topology) circuit with noise

figure less than 6dB and voltage conversion gain of 13dB.

o Switched Capacitor BPF with gain of 20dB and Q of 5 around

2KHz and sampled clock of 100 KHz.

. MMIC Designs

o C Band Mixer with RF frequency range of 5.7GHz to 5.9GHz, LO

frequency range of 5715MHz to 5865MHz, and IF frequency range

of 0.5MHz to 20MHz. Mixer designed to have max conversion

loss of 3dB and max LO/RF isolation of 16dB.

Skills Profile

. Circuit Design Tools: Cadence Virtuoso Platform version 6.1 and 5.1

(schematic, analog design environment, layout, Assura LVS, and

Assura RCX), Advanced Design System (ADS), AWR MicroWave Office,

SPICE, ASITIC

. Programming Languages: C, C++, Ocean Script

. Applications: Visual Studio 6.0, Visual Caf 4.1, Microsoft Office,

MATLAB, Mathematica, Syntricity Data Conductor

. Lab Tools: Oscilloscope, Signal Generator, Spectrum Analyzer, VSA,

High Impedance Probe

Background

Member of Tau Beta Pi Engineering Honor Society

References

Available upon request

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