Alvin Sugerman

Semiconductor Device/ESD Engineer

***** ******* **.

Thornton Co. 80602

***-**-****

abl8c6@r.postjobfree.com

** **** *********** ************* ******/ESD Engineer seeking part time remote, via computer and

tele-communications, employment as ESD Semiconductor Engineer, 16 hours/week

Education

MA, Physics, 1966, Belfer Graduate School of Science, Yeshiva U., N.Y., N.Y., and most Ph.D. level

courses completed.

BS, Physics, 1964, Adelphi U., Garden City L.I., N.Y.

1997-6/2009, at Fairchild Semiconductor, South Portland Maine (Principal Engineer)

ESD process/device solutions were provide for 0.8um to 0.35um technologies. I have been a major

resource of information and thinking for the company on the subject of ESD and latch-up. My ESD and

Latch-up responsibilities include design of new devices, simulating them with CAD tools Suprem and

Medicci (d-c and pulsed), do sanity checks with back-of-the-envelope calculations, electrically bench test

them using HP4156, TLP and Pulse Generator, statistically analyze results using JMP and write summary

reports, provide planning for DOE Device/Circuit Test Patterns and supervise their layouts, write the ESD

and Latch-up rules in the Technology Specification and assist in coding these rules. I also consult with

my colleagues on ESD and latch-up in general. After the technologies pass progressive development

phases, I continue to act as consultant to circuit designers and process engineers responsible for and to

improve older technologies. My responsibilities have included supervising and teaching ESD and Latch-

up skills and concepts to new engineers.

Typically new technology processes require new ESD devices. Providing such devices necessitates an

in-depth knowledge of device physics in relation to the process . I have provided snap-back and non-

snap-back solutions when violation thereof can cause latch-up, R-C gate triggered low voltage isolated

ESD nmos wherein capacitively coupled gates provide the large drain current required to lower the

avalanche drain voltage, engineering of lightly doped drain/source implant to reduce series resistance and

increase emitter injection efficiency, cascoded ESD nmos and the cascoded scr for large current carrying

device capability and ESD nmos-diode for non-snap-back solutions. I introduced ESD implant at the drain

and source to lower trigger points by decreased channel lengths, higher emitter efficiency and higher

drain electric field, FET circuits to lower the voltage trigger point for ESD npn, and self protecting circuit

triggered LNDMOS drivers that stay within SOA. These accomplishments were done in cooperation with

my colleagues. Dialog with the designers and with the application engineers to more accurately define the

operational voltage windows for ESD. There were generic ESD solutions and solutions tailored to specific

circuit needs. When project requirements change mid-stream, I quickly adapt and provide timely

solutions.

Honors

Designated as a “Key Technologist”: 2001-2004

Presented papers at the Fairchild Technology Conferences in Hawaii “Similarities and Differences in

Analog and Logic ESD Solutions”, in Phoenix “ESD Snapback Solutions”

“Development of a Multi-Market 0.35 um Semiconductor Process Technology Family

2004 ASMC ” with S.Leibiger, et.al.

Author and co-Author of Patents:

“Internally Triggered Electrostatic Device Clamp with Stand-off Voltage”, patent# 6646840,

with M. Harley-Stead and R. Roberts

“ESD Protection for Semiconductor Products”, with Jun-Cai and S.Park, patent# 6873017

1993-1997, at National Semiconductor, South Portland Maine (Principal Engineer)

AlCu Deposition and Characterization using Varian M2000.

Responsible for bringing up sputter deposition tool, characterizing tool performance and thin film material

Co-author of external paper

28 years, 1966-1993, at IBM Hopewell Jct & Yorktown Watson Research Center, N.Y. (Senior Engineer)

Basic Semiconductor Device Engineering. Special device development: mathematical characterization of

vibrating semiconductor cantilever for sound/electrical conversion, mathematical optimization of photo

diodes, lateral npn improvements, statistical evaluation and tracking of resistors, Schottky diode formation

and evaluation for various process innovations (e.g.: RIE, thin oxide reduction, metal-metal reaction),

various metal deposition techniques with enhanced ion content.

Honors

Division award, 1988

Taught graduate level semiconductor physics classes at IBM for three semesters.

Guest Editor IBM Research and Development Journal: Topical on Schottky Barrier Diodes.

IBM mentor projects for PH.D. students at Stanford University and Rensselaer Polytechnical University.

Author, co-author and presenter of approximately 15 external papers.

Two IBM patents

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