Design Project

Lin Zhang (Availability: July *, ****)

____________________________________________________________________________

__

Contact: *** **** ****** **, ****: (903)366-

2953

Apt 167H, Email:

********@***.*****.***

Amherst, MA 01002,

http://www.people.umass.edu/linzhang/jbsk/

Objective: Seeking an engineer position in circuit and system where my

exceptional knowledge of Analog,

VLSI and RF design/test will be fully utilized.

Qualification: -4 years working experience of Electrical

Testing/Application and Software Development in c/c++.

-Experience of Analog/Mixed signal circuit and system design,

including operational amplifier, current reference, bandgap,

gain boosting circuit, switched capacitor low pass filter.

-Experience of Power Management IC design, including LDO, DC-

DC converter and SMPC.

-Experience of Digital/VLSI/Embedded system design especially

RTL/Physical design.

-Experience of Microwave/RF transceiver chain design and lab

instrument metrology, including LNA, Mixer, VCO, BPF, PA, VGA,

Antenna.

-Self-motivated researcher, fast learner, creative problem

solver and friendly team player.

Education: The University of Massachusetts Amherst,

Amherst, Massachusetts

Ph.D Candidate in ECE, Full Financial Support, (Jun 2009-

Present) GPA: 3.7/4.0

The University of Texas at Dallas,

Richardson, Texas

MSEE in Microelectronics, (Aug 2007- Dec 2008)

GPA: 3.7/4.0

Fuzhou University,

Fuzhou, China

BE in Telecommunication Engineering, (Sep 1997-Jun 2001)

GPA: 3.5/4.0

Project/Course Summary

. Power Management Circuit Project: Low-Dropout Regulator (LDO) Design

A low-drop out (LDO) regulator is designed and simulated with TSMC 0.35um

process using HSPICE. Low output impedance buffer stage and Miller

Compensation are used. Over 60 degree phase margin is achieved under full

range of the load current from 0mA to 55mA. Total quiescent current is

35uA. Maximum undershoot and overshoot is 110mv and the recovery time is

1us. A bandgap circuit is designed to provide the reference voltage of

0.8v.

. Analog IC Design Project: Design of a Two-Stage Operational Amplifier

Design a two-stage amplifier in TSMC 0.35um process to meet specifics of:

Differential voltage gain Avd>80dB; Output voltage swing range OVSR>

2.2V; Slew rate>10V/uS; ICMR>2.2V; CMRR>60dB; UGF>25MHz; Phase margin

PM>60; Power dissipation Pdiss<1mW.

. Advanced Analog System Project: Design of a 4th Order Switched-Capacitor

Low-Pass Filter

Design a 4th order switched-capacitor low-pass filter including switches,

amplifiers and current references with TI CMOS 1um process using HSPICE.

The design is to meet: clock frequency=500kHz, filter corner

frequency=5kHz, Output swing=3.5 Vpp with 5V supply, PSRR>40dB at 5kHz

from VDD, Output Noise<70 u Vrms, THD<-70dB.

. Advanced Analog System Project#2: Design of a 5-bit R-2R Ladder

D/A Converter

Calculate the ideal VLSB and Quantization Error Deviation. Design switch

sizes so that there is less than 1/4 LSB IR Drop across them when they

are on and those sizes should be chosen to give the best linearity. Check

the output voltage error due to LSB and MSB resistors mismatches

respectively. Plot the INL and DNL.

. RF IC Design : VCO Design for WIMAX Transceiver

Front-end analog circuit blocks and system level design knowledge are

discussed in this course: Transceiver System Design---Link Budget

Analysis, Low Noise Amplifier (LNA), Mixer, Voltage Control Oscillator

(VCO), and Power Amplifier. In course project, a VCO of super hyterodyne

transceiver for WIMAX is designed using Agilent ADS.

. Microwave Metrology: Use Agilent and HP instruments to characterize

microwave devices and systems

1) Use Agilent E5062A network analyzer to measure the downconverter's

amplifiers and filters. Use the Agilent spectrum analyzer to measure the

conversion loss of the mixer.

2) TRL Calibration and Probe-Based Measurement.

3) Noise measurement of downconverter using Y-Factor and Noise Figre

Meter.

4) Characterize the distortion of the downconverter, OIP3, P1dB, SFDR

etc.

5) Phase Noise measurement using Spectrum Analyzer, Delay Line

Discriminator, Phase Noise Meter methods.

6) I&Q modulation and demodulation measurement in both Time and Frequency

domain to establish the relationship between them.

. VLSI Design Project:

RTL Design of a Pinball Machine using Behavioral Verilog. Test bench is

made to test the function of this FSM. Draw gates' schematics and layout

in Cadence Virtuoso, perform DRC/LVS/RCX in Assura. Logic synthesis

transforms the RTL design into standard cells. Gate level netlist is made

based on standard cells. Verify that the Structural Verilog functions the

same as the Behavioral Verilog. Auto place and route the netlist using

Encounter. Do power estimation, lib/lef generation. Post-layout

simulation using Virtuoso Spectre. Do Timing analysis using PATHMILL on

the circuit extraction to get signal paths for critical path evaluation.

. Advanced VLSI Design Project:

Use Cadence to Design and layout a 256b SRAM using the IBM 130nm process.

Design, implement, layout and simulate a 14b X 14b multiplier.

. DSP Architecture:

Learn hardware and software knowledge related to DSP processor

architecture which include processor products of Texas Instrument, Analog

Device, ARM and StarCore. Learn Software Pipeline technique to improve

processor's working efficiency at software level manually. In the course

project, 4 different methods including "Recursive method", "DIT Radix-2",

"DIF Radix-2" and "DIF Radix-4" are used to implement FFT in TI's CCS

FET2 'C6000.

. Advanced Digital Logic Project:

Build up a sequential circuit using Verilog. Synthesize and optimize the

circuit by Design Analyzer. Replace normal Flip-flops by scan ones.

Generate test protocol file and save the new architecture with scan

cells. Read the verilog architecture file and the protocol file by

invoking TetraMAX and then build the ATPG model. Perform design rule

check and then run the ATPG to report faults and patterns.

Working Experience:

May 2004-Oct 2005 Software and Networking Engineer, Fu Zhou City

Commercial Bank Fuzhou, P.R.China

Do the project of "Transaction in Local Area" using C/C++. Design the

transaction GUI. Setup the test pattern and test strategy by using HP

Test Director. Report defects and fix problem.

July 2001-May 2004 Electrical Engineer, Fujian TV News Channel,

Fuzhou, P.R.China

Design and test the first HD Digital Broadcast Mobil System of Fujian TV

Station.

Feb 2001-Jun 2001 Network Access Design Intern, China Telecom

Fuzhou P.R.China

Project: Investigate and design the Broadband Network Access for the

community KangShan using AUTO CAD.

Simulation Tools: Hspice, Cadence, Agilent ADS, Ansoft Designer;

Coding & Software: Verilog/VHDL, C/C++, Python, Perl, Java, Assembler, DLX,

TI-TMS320C64x, ARM, SHARC, Matlab, Test Director, AutoCAD, Microsoft Office

(Word, Excel, Visio, Front Page, Powerpoint);

Lab Equipments: Probe Station, Signal Generator, Oscilloscope; Agilent and

Hp Spectrum Analyzer, Power Meter, Network Analyzer.

Contact this candidate