Design Assistant
Resume:
ABHIJIT SIL
**** ********** ****, ********* **********, Apt # 3021, Folsom, CA-95630
Mobile - 337-***-**** Email : **************@*****.***
Education:
Doctor of Philosophy in Computer Engineering
Fall 2010(expected)
The Center for Advanced Computer Studies (CACS),
GPA - 3.888
University of Louisiana at Lafayette
Master of Science in Computer Engineering
Fall 2007
The Center for Advanced Computer Studies (CACS),
GPA - 3.857
University of Louisiana at Lafayette
Master of Science in Electrical Engineering
Summer 2005
Minnesota State University, Mankato
GPA - 3.91
Bachelor of Engineering in Electronics & Communication
2002
Visvesvaraya Technological University, India
GPA - 3.12
Software Exposure:
Operating System: Windows 2000/XP, Linux, Sun Solaris
Programming Languages: C, C++, Java
HDL's: Verilog, VHDL
Scripting Language: Tcl, Perl
EDATools: HSpice, Spectre, Nanosim, Model-Sim, Design Vision, Design
Compiler, Prime Time, Encounter, Calibre, Star-RCXT, Cadence Virtuoso,
Magic, Tsuprem.4, Lasi7.0, Multisim,
Software Package: MatLab
FPGA Tools: Altera MAX PLUS II, Xilinx ISE
Work Experience:
1. Project Trainee at Defense Research & Development Organization (DRDO),
Bangalore, India in the field of Digital Signal Processing. Feb 2002 -
July 2002
2. Graduate Teaching Assistant, Electrical & Computer Engineering Dept,
Minnesota State University, Mankato.
. Lab instructor for IC Fabrication Lab - Fall 2004
. Lab instructor for Solid State Lab- - Fall 2004
. Lab instructor for VLSI Design Lab - Spring 2005
3. Graduate Teaching Assistant, The Center For Advanced Computer Studies,
University of Louisiana, Lafayette.
Teaching assistant for VLSI Design and VLSI Architecture - spring
2007 to present
Honors:
. Third place winner in IEEE CS Student Chapter Paper Contest, 2010.
. Second place winner in IEEE CS Student Chapter Paper Contest, 2008.
. Honored for Academic Excellence, University of Louisiana, Lafayette,
2007.
. Winner of IEEE CS Student Chapter Paper Contest, 2007.
. Merit Scholarship holder for Academic Excellence for securing position
in top 1% (out of 350,000 students approximately) in State Level High
School Certificate Exam, 1998.
Organization:
. IEEE Student Member (National)
. IEEE-CS UL student chapter secretary
Publication:
. Abhijit Sil, Harsha Yelisala, Priya Gadde, Magdy Bayoumi, "Energy-
Efficient MAC Unit for Ultra-Low Power DSP Applications", Journal of
Low Power Electronics (Under Review)
. Abhijit Sil, Krishna Balusu, Chandrasekhar Guram, Magdy Bayoumi, " A
3.1GB/s 8Kb Zero Precharge, Pipelined Highly Stable 2-Port 8T SRAM
Design in 65nm", IEEE Transactions on (VLSI) Systems(Under Review)
. Abhijit Sil, Magdy Bayoumi, "A Bit-interleaved Dual-port Subthreshold
6T SRAM Array With High Write-ability and SNM-free Read in 90nm
Technology",Journal of Low Power Electronics(Under Review)
. Abhijit Sil, Krishna Balusu, Venkat Yalamanchili, Rajesh Reddy Challa, Neeharikha Gogineni, Magdy Bayoumi, "An Energy-Efficient 32-bit
RISC Processor for Sensor Platform in 90nm Technology", Journal of Low
Power Electronics (Under Review)
. Abhijit Sil, Neeharika Gogeneni, Soumik Ghosh, Magdy Bayoumi, "A
Novel High Write Speed, Low Power, Read-SNM-Free 6T SRAM Cell" IEEE
MWSCAS, August,2008, Knoxville
. Abhijit Sil, Eswar Prasad Kolli, Soumik Ghosh, Magdy Bayoumi, " High
Speed Single Ended Pseudo Differential Current Sense Amplifier for
SRAM Cell", IEEE International Symposium on Circuits and Systems,18-
21 May 2008, Seattle
. Abhijit Sil, Soumik Ghosh, Magdy Bayoumi, "A Novel 8T SRAM Cell with
Improved Read-SNM",IEEE MWSCAS/NEWCAS, August 4-7,2007, Montreal,
Canada
. Sherine AbdelHak, Abhijit Sil, Yi Wang, Magdy Bayoumi, "Reducing
Misprediction Penalty in the Branch Target Buffer " IEEE
MWSCAS/NEWCAS, August 4-7,2007, Montreal,Canada
. Abhijit Sil, Soumik Ghosh, Magdy Bayoumi, "A Novel 90nm 8T SRAM With
Enhanced Stability" IEEE International conference on IC Design &
Technology, May 2007, Austin
Project Details:
Innovative SRAM Memory Chip Design: My work is devoted to design different
SRAM cell depending on their target application. Following are the topics
accomplished in this field.
o Single ended pseudo -differential current sense amplifier is
proposed in 90nm.
o Design 4 Kb sub-threshold 6T SRAM chip which can operate at
210mV and can also be used for bit-interleaving structure in
90nm.
o Design 4 Kb sub-threshold 7T SRAM chip which can operate at
170mV with high standby SNM and can also be used for bit-
interleaving structure in 90nm.
o Design 8Kb high-speed pipelined 8T SRAM chip with bit-
interleaving structure in 65nm.
o 4Kb conventional 6T SRAM array chip fabricated in 0.5um
technology.
Ultra-Low Power Processor Chip for Sensor Platform: In this work, I guided
a group that designed an energy efficient 32-bit RISC processor. The design
was targeted for branch and data intensive computations. The design
included both architectural and circuit techniques to optimize energy
consumption. An advance branching technique was introduced to reduce stalls
in branch intensive applications, which in turn decreased energy wastage
due to incorrect branching decision. Architectural innovation also included
low power data memory access policy. On the circuit front, energy
consumption was minimized by scaling down the supply voltage near to
threshold. The 24 Kb memories incorporated sub-threshold 6T SRAM cell to
ensure read stability at sub-threshold voltage down to 180mV. The design
has gone through the different stages of ASIC flow, such as, RTL coding,
behavioral verification, synthesis, post synthesis timing, floor planning
and custom layout, post layout timing, DRC, chip level verification.
Sub-threshold MAC Chip Design: In this work, I led a group that
investigated different logic families that are suitable for sub-threshold
logic circuit operation. Several logic gates layout were specially designed
for below sub-threshold operation. Finally sub-threshold 17bit MAC chip was
designed using dynamic threshold pass transistor logic at below 200mV
voltage in 90nm technology.
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