Engineer Design

Oleg Korobeynikov

**** ******** ** #**, **********, MA 01907

Phone: 781-***-****, 781-***-**** (mob)

E-mail: *********@*****.***

OBJECTIVE: Mixed signal ASIC design, communication systems, DSP.

EDUCATION:

1977-1983 Moscow Institute of Physics and Technology.

Qualification: Master of science Engineer-physicist, IC design.

SKILLS:

Schematic design/simulation/layout RF, Analog and Digital components,

transistor level design, project verification (DRC/ERC/LVS, parasitic

extraction).

Synthesis(Verilog/VHDL), RTL-design, digital cells routing, IO-cells

design, FPGA design.

Experienced with PC and SUN station: "Mentor Graphics" ("Calibre", "Eldo"

"HDL Designer", "ModelSim", "Leonardo"), "CADENCE"(Analog artist/Virtuoso),

"Hspice", "Tanner EDA", Matlab/Simulink, C, Tcl.

HIGHLIGHTS OF QUALIFICATION:

- 20 years ASIC digital and mixed signal IC's

- 6 years Communication/DSP

- 8 years RF and Analog mixed signal IC's

EMPLOYMENT:

"Panavision Imaging, LCC" (Homer, NY, USA).

2010 - Imaging IC design, IC Design Engineer.

Design of the imaging sensor IC for video application - 6xHDTV resolution,

12-17 Mpix, 48-120 fps (A/D 10-12 bit, Dynamic Range ~70dB, 4-8 el. rms

noise, clock ~200 MHz, Power ~4 W).

"Custom One Design Inc." (Melrose, MA, USA).

1999-2009 - RF and Analog mixed signal IC design (0.18 um CMOS), Senior RF

Design Engineer.

Chip designs

- Single chip CMOS Direct Conversion Tranceiver (1.4 GHz RF-

components), single chip low-IF CMOS GPS-receiver (3.5 GHz RF-

components) - Sigma-Delta Frequency Synthesizer, PLL,

Subharmonic Mixer, Phase shifter, Prescaler. Special high

symmetrical RF-Mixer layout for harmonics and noise suppression

- results on silicon was better than simulation. Symmetrical

baseband layout to minimize I/Q-distortions. Component isolation

(digital, analog, RF). CML-logic for RF-applications - frequency

division 5 times faster than CMOS, low-noise. Special low noise

Digital Library and Pads for mixed signal application.

- Design of the Sigma-Delta ADC for CAT-scanners - the most

precision solution for image sensors array readout - High-

precision analog components, SC-circuits design, suppression

noises (kT/C, 1/f, OpAmp noise), SC bandgap voltage reference

(no resistors), DSP-part, transistor level design.

- Mixed signal chip for Blood sugar meter for "NOVA", design works on

first silicon. Design includes DC-DC convertor, power transistors, A/D

convertor, OpAmps, digital part.

Multi-phase oscilator and phase grid generator for UWB-radars and Radio

Imaging - 256 phases, step 20ps, jitter<3.5ps

Layout design:

1. I/O cells layout - I/O cell library, LVDS-pads, ESD-protection, RF-

ESD, Pad Ring design. Layout provide uniform current distribution to

avoid overload ESD-protection.

2. Digital layout - Standard Cell Library, Place and Route, clock tree

generation, high frequency layout, fast CML cells for RF applications

- frequency division 5 times faster than CMOS.

3. Array layout - RAM/ROM/Image sensors array layout

4. RF/Analog layout

Automatic generation of the component's layout

- RF /Analog transistors (including guard rings)

- MIM-Cap

- Inductance

manual routing of the RF/analog components. This approach allows to

get good correspondence between component's layout and spice models,

results are relatively independent on layout person.

Special technic to improve device matching for analog components

(centroid).

Special high symmetrical RF-layout for harmonics and noise suppression.

RF-layout - LNA, VCO, Mixer, AGC, PA, PLL, CML-prescaler and Phase shifter,

RF-IOs.

High frequency layout, minimization of parasitics, shielded buses, I/O

cells with low EMI radiation.

Symmetrical baseband layout to minimize I/Q-distortions.

Component isolation (digital, analog, RF). Triple well isolation. Substrate

noise reduction. Low noise digital library and I/O cells.

High voltage layout (LDMOS, component isolation, latch-up prevention),

radiation hardened layout.

Top level floor-plan and routing, power/GND buses distributions, clock

buses distribution.

Layout of wires to meet RC and characteristic impedance requirements,

critical path routing.

Calculation of power supply bus IR drop and electro-migration analysis.

Project verification (DRC/ERC/LVS, parasitic extraction).

"MIEE"(Zelenograd, Moscow, Russia)/"Ericsson" (Stockholm, Sweden)

1994-1999 - Spread spectrum communication systems (CDMA) - DSP - Hilbert

transform, cos/sin-filters, Complex Multiplication, FIR - Band Pass/Low

Pass, PLL, direct frequency synthesis, acquisition and tracking units,

digital Intermediate Frequency (IF) unit, Subsampling receiver, capability

to work in high-noise environment.

"Nauchny Center" (Zelenograd, Moscow, Russia)

1993-1994 - Optoelectronic CMOS IC for adaptive optics and for satellites

observation systems. Image sensors array design.

"MIEE"/"Nauchny Center" (Zelenograd, Moscow, Russia)

1990-1993 - Design data-processor for Massively Parallel Processor

architecture of SIMD type (similar to Connection Machine). Design

functional circuit of 32-bit RISC-processor. Design VLIW-architecture for

digital signal processing. Design of the different processor's units -

FastAdder/Multiplier/RegisterFile. Data-Path design.

"Exiton" (Pavlovsky-Posad, Moscow region, Russia).

1988-1990 - Radiation hardened CMOS ASIC design, high-voltage CMOS design.

"Moscow Institute of Physics and Technology" (Moscow, Russia).

1984-1988 - High-speed bipolar IC design for vector supercomputer (similar

to Cray).

EMPLOYMENT HISTORY:

2010 - "Panavision Imaging, LCC" (Homer, NY, USA). IC Design Engineer,

Imaging IC design.

1999-2009 - "Custom One Design, Inc." (Melrose, MA, USA). Senior RF Design

Engineer, RF and Analog mixed signal IC design.

1994-1999 - "MIEE"(Zelenograd, Moscow, Russia)/"Ericsson" (Stockholm,

Sweden). Chief of group, spread spectrum communication systems design.

1993-1994 - "Nauchny Center" (Zelenograd, Moscow, Russia). Leading

engineer, ASIC design.

1990-1993 - "MIEE"/"Nauchny Center" (Zelenograd, Moscow, Russia). Leading

engineer, microprocessor design.

1988-1990 - "Exiton" (Pavlovsky-Posad, Moscow region, Russia). CMOS ASIC

designer.

1984-1988 - Moscow Institute of Physics and Technology (Moscow, Russia).

High-speed bipolar IC designer.

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