Project Power

Srikanth Kulkarni

E-mail:

********@*******.******.***

Phone: 208-***-****

OBJECTIVE

Pursuing a challenging job where I can apply my skills and forward my

knowledge while contributing towards the growth my employer.

SUMMARY OF QUALIFICATION

. I have four years of experience of maintaining and woking in a

clean lab

. I have experience in die-attach, wire bonding and encapsulation

processes

. I have experience with thin film deposition and etching processes

. I have experience with thick film deposition (screen/stencil

printing) process

. Experience in design of experiments and statistical analysis

. Knowledge of packaging concepts and design issues

. I have studied semiconductor fabrication process and issues in

detail

. Ability to learn and adapt to work environment.

. Good communication skills and interpersonal skills, ability to work

effectively as a part of a team. Quick learner and hard worker with

a "can do" attitude.

EDUCATIONAL SUMMARY

University of Idaho M.S. in Electrical 3.5

Engineering

Visveswaraiah Technological B.E. in Electronics and 3.6

University Communication

PROJECTS

. High Power High Temperature Package with SiC switches: In this project,

our group is responsible for designing and developing a 3-phase inverter

module with SiC JFET/MOSFET switches with a voltage and power rating of

600V and 30KW for operation at 200 C junction temperature. My role in the

project includes literature survey, selection of materials, design and

simulation of electrical and mechanical performance of the module, process

design and developing the power module.

. SiC Die Attach (Thesis Project): I investigated suitable materials and

processes for reliable die attach technique for SiC die and DBC substrate

for high power, high temperature (>200 C) application. The criteria for

section of materials for die attach was based on the requirements for high

power and high temperature power packages. To evaluate each die attach

material, die attach samples were made with SiC dies and DBC substrates by

vacuum soldering process. To test the reliability of the die attach

materials, thermal cycling and high temperature storage were performed on

the samples. The range of materials that we have considered for the

application include, lead based and lead free solders in the form of

performs and polyimide based adhesives. As a continuous effort to find

better die attach materials and technology, we are currently investigating

Silver nanoparticles and diffusion soldering process.

. Substrates for High Temperature, High Power operation: We are

investigating the reliability of the substrates at operating temperature

of the power modules. The substrates materials that are chosen for

investigation are DBC with different ceramic materials such as Al2O3, AlN,

Si3N4 and DBA for various metal-ceramic thicknesses. Stress analysis is

done for the substrates using ABAQUS FEA tool. To support the simulations,

the substrates are subject to thermal cycling to observe common modes of

failure such as delamination. Effect of dimples and exposure to forming

gas at reflow temperature is also studied in the project. The reliability

of bonding between substrates and various baseplate materials such copper

and AlSiC is also studied.

. Wirebonding, Encapsulation and Housing for High Power and High

Temperature Operation: The project involved identifying candidate

materials (polymers) with high breakdown voltage and high operating

temperature. We have assessed the effect of treatments such as thermal

cycling and high temperature storage on candidate encapsulation and

housing materials. In this work detailed study of the polymers was done

with thermogravimetric analysis and differential scanning calorimetry.

Effect of encapsulation on aluminum wirebonds during operation was studied

by thermal cycling.

. Low Temperature Co-fired Ceramic: The project involved providing better

thermal management for a power diode using liquid coolant. A substrate

that was made using Low Temperature Co-fired ceramic was chosen for this

purpose. The issues dealt with in the project were die attach and

implementing a heat exchange fluid conduit in the substrate. A set of

experiments were conducted to test the reliability of die attach and the

heat exchange fluid conduit.

. Packaging of a High Power Inverter: This project addressed die attach,

wire bonding, encapsulation and sealing aspects of packaging a multichip

module. Several JFETs and Diodes were connected in parallel to increase

the current handling capacity and therefore the power capacity of the

inverter package. The issues that were taken into account were thermal

management, dielectric breakdown and thermal shock induced stress in the

package.

. Thermal management in a Multi Chip Package (Course): The project involved

designing a multi chip package for an inverter circuit. The components

were SiC dies and the substrate chosen was DBC. Designing least resistance

paths for electric and thermal conduction in the package were the some of

the considerations in the projects.

WORK EXPERIENCE

. Working as a Graduate Research Assistant in Idaho Microelectronics

Laboratory (IML) at the University of Idaho.

. Experience work with LTCC, ESD, Thermal analysis, mechanical stress

analysis, encapsulation issues, die attach issues, accelerated aging

techniques (High Temperature Storage and Thermal Shock Testing), testing

techniques (shear and pull test), designing and conducting experiments.

. Assisted Dr. Fred Barlow in setting up a clean lab for IML.

. Designed and conducted several experiments for various ongoing projects

in IML.

. Quarterly and monthly reports for the sponsors of the ongoing projects to

apprise of the progress.

. As the senior student of IML, coordinated with less experienced students

to meet the deadlines on several projects.

RELEVANT COURSES

> Introduction to Microelectronic Packaging

. Thin Film Fabrication

. Power Electronics

. Microelectronic Fabrication

. Memory circuit design

. Analog Filter Design

. Electronic circuits

. Signals and Systems

. Signal Processing

. Statistical Analysis

SKILL SET

. Tools - ANSOFT Q3D extractor (parasitic extraction tool), Abaqus FEA,

AutoCAD, MathCAD, Spice, MS Word, Excel, Project, PowerPoint

. Lab Equipment - Wafer Dicing saw (Disco DAD 320); LTCC Punching machine

(UHT MP-4150); Vacuum Soldering System (Scientific Sealing Technology

3130); Evaporation & Sputter Deposition system (Kurt J. Lesker PVD-75);

Shear and Pull Testing machine (Condor XYZtec); Thermal Shock Test

machine (Espec-TSE-11-A)

PUBLICATIONS AND PRESENTATIONS

. "SiC & GaN Die Attach for Extreme Environment Electronics", Srikanth

Kulkarni, Fred Barlow, Aicha Elshabini, and Rick Edgeman, Proceedings of

the 2008 International Microelectronics and Packaging Conference,

Providence, RI, November 2008, pp. 1119-1125.

. "Encapsulation of Power Modules for Extreme Environments", Gona Rao,

Srikanth Kulkarni, Fred Barlow, and Aicha Elshabini, accepted for

publication in the Proceedings of the 2009 International Microelectronics

and Packaging Conference, San Jose, CA, November 2009.

Contact this candidate