Design Electrical
Resume:
SHWETA GUPTA
213-***-****(M)
Los Angeles, 90007, CA
abl3ge@r.postjobfree.com
Objective: Securing an intellectually challenging engineering position in
a fast paced work environment where I can contribute to my fullest towards
the overall progress and growth of the organization.
Areas of Interest: High performance & low power circuit design, HDLs and
RTL coding, design and simulation of schematics and layouts using CAD tools
like Cadence and ePD, floor planning & DRC and LVS checks, ATE, DFT
including BIST, SCAN, fault modules, ATPG and fault simulation,
semiconductor physics & chip fabrication.
Education
Master of Science in Electrical Engineering (Digital VLSI & Computer
Architecture)
University of Southern California, Los Angeles, CA
May 2010
Bachelor of Engineering (Electronics)
S.R.K.N. Engineering College
RTM Nagpur University, Nagpur, MS (India)
May 2008
Work Experience
Summer Internship-Training Program (IIT-Guwahati), June-July 2009
Introduction to Robotics (Embedded system design) and Embedded C.
Dealing with 8051 and AVR Microcontrollers, their architecture and
programming, exposure to different communication protocols, designing and
interfacing different kinds of sensors, actuators and motors.
Hands on 12 different types of built-in Real time Robots.
Technical Skills
Programming Languages : C, C++, VHDL, Verilog, Perl, HTML
Assembly Languages : Microprocessor/ Microcontroller 8085, 8086,
8051
Software Tools : Hspice, Cadence, MATLAB, Cacti,
estate estimator, ePD, Simulink, modelsim, pcb
Express, Multisim, 8085 Simulator
Platforms : Unix, Mac OS X, Solaris,
Windows 9X/NT/XP/2000/Vista/Win7
Applications : MS Office, Adobe Photoshop,
Internet Browsers
Relevant Course Work
Digital VLSI : MOS VLSI Circuit Design, VLSI
System Design
Computer Architecture : Computer Systems Organization, Computer Systems
Architecture
Design and Test : Diagnosis and Design of Reliable
Digital Systems
Solid State Devices : Solid state Processing and Integrated
Circuits Laboratory, Modern Solid state Devices
Lab Work
Productive hands on experience in a Class 100 clean room of fabricating
3'' silicon chip using processes like thermal oxidation, lithography,
etching (dry/wet) and electron beam metallization followed by studying
electrical characteristics of components so fabricated.
Project Details
Designing and Implementation of a test generation module: A test generation
module was designed and implemented in the form of C code which included a
preprocessor, good circuit simulator, ATPG (automated test pattern
generator), parallel and deductive fault simulators along with D algorithm.
Performance optimization of a processor module: By altering various
parameters and using the cacti tool along with a predefined real estate
estimator the performance was optimized of a processor module with maximum
speed and least transistor count as possible.
SHWETA GUPTA
Page 2
Modeling a 16-Bit Motion Estimator for a DSP: A 16-bit ME kernel assembly
was formed by assembling accordingly designed data pointer, two blocks of
2KB SRAM, 16-Bit registers, 24-Bit registers, 16-Bit absolute subtractor,
24-Bit adder and D flip flop which reads the two 4x4 pixel blocks and
calculates the difference between them. The output is the accumulated
difference for all the pairs of pixels in the two blocks.
Real time PC to PC communication: PC to PC communication module was
designed through wired and wireless means including the hardware using RS-
232 and the code was formulated in C++.
Formulation of a "Quarterback neural network" Assembly: The task was to
analyze required conditions and to design and implement schematic and
layout of Quarterback neural net with least possible area and delay using
Cadence as simulation tool.
Design and Simulation of a Seven Stage pipeline: Functionality of a
pipelined processor was understood and a seven stage pipeline processor was
implemented for the given specifications using ePD as the design tool.
Implementation of 8051 using VHDL: VHDL code for 8051 was written along
with its test bench followed by simulation of the code using Modelsim.
Implementation of a 16-bit RISC CPU: VHDL code for 16-bit CPU was written
along with its test bench followed by the simulation of the code using
Modelsim.
Microcontroller Based Bidirectional Visitor Counter: The said circuit was
designed followed by its validation by performing bread board testing,
designing of PCB, mounting of components and testing the final circuit
hardware.
Leadership/Organizations
Member, Institute of Electrical and Electronics Engineers (IEEE)
2010-2007
Aced the robot making competition in the Robotics Summer Internship Program
(IIT-Guwahati) 2009
Won 2nd prize in Ad Making competition in WAD (Workshop on Aptitude
Development) 2007
Presented a paper in National level Technical symposium- 'ICON-2006'
2006
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