Objective:
To pursue a career in electronics manufacturing industry where my skills,
expertise and knowledge would be utilized
Education:
Doctor of Philosophy in Industrial and Systems Engineering, State
University of New York at Binghamton,
Expected Date of Graduation: August 2010 (GPA: 3.7/4.0)
Dissertation Title: Resource and Production Planning - Post ERP
Implementation at an EMS Provider
Master of Science in Industrial Engineering, State University of New York
at Binghamton, USA, December 2007
(GPA: 3.67/4.0)
Thesis Title: Evaluating and Improving Pad Robustness under Lead-Free
Environment
Bachelor of Science in Mechanical Engineering, Xi'an Jiaotong University,
China, May 2005 (Aggregate: 82%)
Bachelor of Science in Business Management, Xi'an Jiaotong University,
China, May 2005 (Aggregate: 89%)
Skill Highlights:
. In depth knowledge of electronic materials properties, assembly
processes development, packaging and interconnect techniques,
metallurgy, thermal and mechanical stress analysis.
. In depth knowledge and experience ofwith Lead-free process development,
materials selections, and assembly design for manufacturing.
. Research, identify and document new PCB and advanced packaging
processing technologies. Provide technical leadership and coordination
for manufacturing in qualification and introduction of new assembly
technologies and equipments.
. In depth knowledge of Lean & Six Sigma, Kaizen, Statistical Process
Control (SPC), Design of Experiments (DOE) and other quality control
tools. Certificated by Lean and Six Sigma Black Belt at Sanmina-SCI,
2009.
Working Experience:
Senior Research Engineer
09/2007 - 09/2009
Sanmina-SCI, San Jose, CA
Graduate Research Intern
12/2005
- 08/2007
Area Array Consortium, Unovis Solutions, Binghamton, NY
Key Research Projects:
01005 Passives Assembly Process Development
. Developed and provided the mass production solution for assembly 01005
passive components, including assembly process development, stencil
design, PCB pad design and equipment selections.
. Company won a $ 180 million contract by showing the customer the
capability of assembly 01005 type passive components.
Wave Soldering Issues Aassociated with OSP Surface Finish
. Investigated both OSP coating properties (materials, thickness & micro-
etching levels) and board design factors (pin-to-hole ratios) impacts
on hole-fill penetration at wave.
. In order to avoid using Nitrogen, a tinning process was developed for
125 mils boards with OSP surface finish and adequate hole-fill was
achieved.
Pad Robustness Evaluation for Pad Cratering Issues
. Investigated and evaluated the impact of assembly process, design
factors (pad design, micro-via, BGA location), laminate materials on
pad robustness.
. Developed the evaluation standards for evaluating pad robustness via
pad strength and fatigue resistance measurements under various
mechanical loading conditions.
. Investigated long-term degradation mechanisms of laminate materials and
further investigated the adhesive & cohesive degradation mechanisms.
Joint Level Mechanical Test Standardization
. Investigated the effect of various test settings on single-destructive
pull test and cyclical-fatigue pull test.
. Investigated the correlation between board level mechanical tests (bend
& drop) and joint level tests by simulating corresponding loading
conditions and failure modes.
. Standardized joint level tests in terms of procedures and parameter
settings according to different loading conditions associated with
certain failure modes.
PCB Laminate Material Evaluation
. Tested and evaluated over 40 PCB laminate materials for lead-free
implementation.
. Developed a PCB material database that stores the information of
survivability for lead-free assembly, pad robustness and degradation
trend evaluation, material hydrophilic evaluation and warpage
measurement.
. Developed a 'quick' method to detect inner layer de-lamination of PCB
by using Shadow Moir to characterize the correlation of PCB warpage
behavior and the damage of laminate materials.
Guideline Document Writing
. Developed a Lead-free Assembly Guideline and Stencil Design Guideline
(Sanmina-SCI); Participated in updating a DFX guideline (Sanmina-SCI).
Quote Model for a Worldwide Application
. Lead a team to develop a Labor Quote Model and deployed globally for
electronic product manufacturing cost appraisal and design trade off
analysis.
Research on Photovoltaic (PV) Cell/ Module Production
. Conducted research on photovoltaic products including solar cells based
on c-silicon and thin film techniques. Defined solar cell and module
assembly procedures including equipment selections and line automation
for high throughput. Developed and implemented a method to measure PV
efficiency.
Other Assembly Process Related Projects
. LGA/QFN voiding issues
. Impacts of reflow cooling rate on second-level joint reliability
. "Head-in-Pillow" issue
. Out-gassing capacitor induced BGA bridging issue
Related Courses:
Advanced Electronic Packaging Design of Experiments (DOE)
Process For Electronic Manufacturing Probability and Statistics
Quality Control
MEMS Packaging Multivariate Date Analysis
Mechanics of Materials Modeling and Simulation
Science of Manufacturing Supply Chain Management
Production Management and Control
Computer Skills:
. Statistical Related: SAS 9.1, MiniTab 15, SPSS.
. Others: Microsoft Office, Arena Simulation10.0, Origin, ANSYS 10.0.,
Professional Societies:
Surface Mount Technology Association (SMTA)
Alpha Phi Mu - Industrial Engineering Honor Society
Reference: Available upon request
Publications:
1. Li, J., Tsai, J., Srihari, K., and Abtew, M., "Improving hole-fill in Pb-
free soldering of thick printed circuit board with OSP finish", SMTA
International Conference, Orlando, FL, 2008
2. Li, J., Srihari, K., and Abtew, M., "Design and process development for
the assembly of 01005 passive components", SMTA International Conference,
San Diego, CA, 2009
3. Li, J., Srihari, K., and Abtew, M., and "Reliability assessment of re-
balled BGAs", SMTA International Conference, San Diego, CA, 2009
4. Roggeman, B., Li, J., Borgesen, P., and Srihari, K., "Assessment of PCB
Pad Cratering Resistance by Joint Level Testing", Electronic Components
and Technology Conference (ECTC), Lake Buena Vista, Florida, 2008