SWAGATH SUBRAMANIAN

Email: abl1kk@r.postjobfree.com, Ph No: 864-***-****

SUMMARY

Focus: Electronics, Semiconductors. Education: Master of Science,

Electrical Engineering. Technologies: Semiconductor Devices, CMOS, ASIC.

EDUCATION

Master of Science, Electrical Engineering (Focus: Microelectronics) at

Clemson University, South Carolina [Dec 09], GPA: 3.62

Bachelor of Engineering, Electrical and Electronics (Anna University) [Jun

07], GPA: 3.62

TOOLS/SOFTWARE AND SKILLS

> Working knowledge with oscilloscopes, DMM and parameter analyzers

> Knowledge of Semiconductor Device Physics and Microelectronic

Fabrications Processes

> Solid knowledge of CMOS device physics

> Working knowledge with EDA tools for schematic capture and layout

simulations.

> Knowledge of Non Volatile Memories.

> Underwent a Clean-room training to evaporate metal to deposit on

surfaces and sputtering process.

> Knowledge of MOSFETs and Transistor level designs

> Working knowledge with commercial Solar cells and thin film devices

> Knowledge of Experimental Statistics

> Circuit and Device Simulators : Hspice, Eldo, B2Spice Version 5

and SILVACO device simulator

> Mentor Graphics Design Suite : Design Architect IC, IC station,

PEX, Calibre XRC

> Waveform Analyzers : Spice Explorer, EZwave

> Hardware Description

Language /Programming : Verilog and C programming

> Packages and Tools : Microsoft Office Suite,

MATLAB, Kaleidagraph

ACADEMIC PROJECTS

Device Physics

> Electrical Measurements on Photovoltaic Devices: Worked on a project

funded by NASA as a research assistant, conducting electrical

measurements on commercial solar cells to model conduction in them.

> Characterization of thin film high-k dielectrics: Electrical

characterization of thin film Hafnium-di-oxide devices by conducting

electrical measurements on them.

> Capacitance-Voltage curves: Simulation of a MOS capacitor at high and

low frequencies using Silvaco.

> Effects of Level 1, 2 & 3 Model Parameters: Studied the device

characteristics of NMOS/PMOS in B2 spice.

IC Design

> Optimal adder design: Schematic design and layout simulation of n-bit

adder circuits using Mentor Graphics IC design tools and compared the

performances and areas of the adder circuits. Implemented n-bit CMOS

adders and developed a figure of merit based on area, power and

performance.

> Customized Hand layout design: Designed inverter layout topologies

such as vertical, horizontal, star connected and donut. Investigated

the effects of RC parasitic on performance of layouts.

> Four bit Synchronous Decade Counter: Schematic design and simulation

of a 4-bit synchronous decade counter using components from self

created library. Implemented the design in B2 Spice using customized

library of gates and obtained layout in Mentor Graphics design suite.

Observed the performance of the layout with and without input/output

pads.

> Cell library design: Designed a library of gates using static CMOS

logic for worst case delay. Analyzed the voltage transfer

characteristic and also effects of variation in temperature, supply

voltage and fan out on gate performance.

Miscellaneous

> Electronic fuse: Worked on the design of an electronic fuse model at

Bharani Electronics, India.

> Floyd's shortest path algorithm: Implemented Floyd's algorithm in C

to calculate the shortest distance between any two points in a graph.

WORK EXPERIENCE/TRAINING

> Characterization Research Assistant, Microelectronic Characterization

Laboratory at Clemson university, Jun 2008- Jun 2009

. Made Test plans and conducted electrical measurements on thin film

devices and commercial solar cells to model conduction in them.

. Worked on the Electrical characterization of high-k dielectric

(Hafnium-di-oxide) thin films.

. Performed a comparative study of three batches of samples that were

fabricated.

> Graduate Teaching Assistant at Clemson University, Aug 2007- May 2008

. In charge of under-graduate level Electronic circuits laboratory.

. Design and Characterization of functional circuits using solid

state devices.

> Project Trainee at Mahalakshmi Systems, India, Jan 2007 - Jun 2007

. Got trained in IC design tools for schematic and layout simulations

such as SPICE and Mentor Graphics design tools.

> Practical Training-Summer at Bharani Electronics, India, May 2006

-July 2006

. Designed an electronic fuse model for protecting appliances using

simple logic circuits and basic passive components.

. Created a Mathematical model to evaluate the reliability of the

electronic fuse using a probabilistic approach in C.

> Program Coordinator Youth Red Cross, India, Apr 2004 -Apr 2007

. As a program coordinator led a team of 15 members while organizing

camps and awareness programs

. Organized blood donation camps in a suburban regions and conducted

awareness programs in schools and colleges around the region.

RELEVANT COURSEWORK: Semiconductor Device Physics- Microelectronic

Processing- Physics and Technology of Passive Electronic Components-

Experimental Statistics-Integrated Circuit Design-Integrated Circuit

Manufacturing-Measurement and Instrumentation

AWARDS AND CERTIFICATION:

> UNIVERSITY OF CAMBRIDGE Business English Communication

> YOUTH RED CROSS award for Service

> UN INFORMATION AND AWARENESS certificate issued by the UNITED NATIONS.

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