Engineer Design
Resume:
Mohammad R. Khan
San Diego, CA 92126
abkxee@r.postjobfree.com
CAREER SUMMARY
Over 13 years technical and team leadership in SOC, ASIC, FPGA, and IP.
Strong record of first pass silicon success.
Low-Power and High-Performance SOC VHDL, Verilog, SystemC,
SystemVerilog
ESL and RTL Platforms Coware Platform Architect,
Design, Integration, and Tensilica
Verification Mentor Modelsim, Synopsys DC, PT
Synthesis, Physical Design, and Atrenta Spyglass, LEC, Debussy
STA Perl, C, C++, Tcl, Java
Methodology, Quality, and EDA
EXPERIENCE
Huawei, San Diego, CA 2008 - 2010
Staff Engineer
SOC Advanced R&D
. Competitive Analysis of Industry and Academic SOC Architectures
. Researched leading edge high performance 4G BTS BB SOC
Architectures
. Provided critical analysis of power, performance, and area with
consideration for application traffic patterns
. Proposed Assertion Based Verification as Many-core NOC
Diagnostic Methodology
. SOC ESL Methodology and Platform Development
. Researched and formulated ESL Methodology for use by US and
China R&D teams
. Proposed "Detailed Cycle Approximate" Analysis Methodology
. Researched State of the Art "ESL Power Analysis" Methodologies
. Designed and Verified RapidIO C++ ESL Models with AXI Interface
. Designed and Verified 2D Mesh NOC Node SystemC Model
. Designed and Verified 1000+ core Tensilica NOC Cycle Accurate
Platform
Texas Instruments, San Diego, CA 2000 - 2008
Senior Engineer
SOC Integration and Verification
. Integrated very high complexity SOC at 65 nm
. Integrated over three dozen Soft-IP (RTL) and over two dozen
Hard-IP (Hard Macro)
. Drove global alignment on IP features and delivery content
meeting quality standards
. Delivered RTL releases meeting aggressive milestones on high
profile program
. Managed I/O Pad RTL, Voltage Domains, Power Domains, Retention
Regions
. Established RTL Integration and Release Methodology for HSDPA, WCDMA,
and UMTS modems
. Integration Specification, RTL Assembly Process, Quality
(Spyglass, LEC, Regression)
. Verified "stacked die" configuration of two SOC using TI Topsim
environment
. Created test cases using C for ARM and DSP
. Integrated and verified 5-FPGA hardware platform in RTL to support
concurrent debug (simulation vs. emulation)
. Simulated DIGRF digital block and SDRAM Controller modules to deliver
test vectors for FPGA platform. Full support of FPGA vectors including
external customer use.
Mohammad R. Khan 619-***-**** Page 2
RTL Module Design and Verification
. Designed and Verified Clock Systems for several CDMA based Modem IP
. Features included: ARM APB & OCP I/F, Calibration, Clock Gating
& Muxing, Reset control, APLL & DPLL control, Interrupts, Pulse
swallowed edge-aligned chip-x clocks
. Created feature-based bottom-up functional test plan. Verified
using VHDL based test bench and hand-crafted test vectors.
Performed code linting, code coverage, and code reviews. Zero
bugs filed against module after tapeout of two devices.
. Performed Synthesis with Synopsys DC and STA with Synopsys PT
. Analyzed clock jitter at Platform level to verify noise requirements
met on clock to DBB
. Published white paper to capture issues and lessons
. Analyzed PLL model to verify Gaussian distribution of jitter
. Supported and guided DFT effort to produce optimal architecture with
maximum test coverage
SOC Physical Design
. Led team of seven engineers to explore and establish a backend
methodology at 90 nm using Magma toolset and TI Pyramid Flow
. STAR-XT for extraction. PT/PTSI for STA/SI
. Executed Clock Tree Synthesis using Avanti toolset and TI backend flow
at .11 um.
. Analyzed first generation silicon layout to optimize PLL vs.
logic placement, reduce cell utilization, and reduce routing
congestion
. Performed STA and SI Analysis using Synopsys PT/PTSI across functional
and DFM corners and operating modes
. Analyzed statistical variance in STA results to better manage
design margins
. Analyzed package process and challenges for stacked die configurations
. Analyzed and Implementation functional ECOs (both script and by hand)
. Analyzed timing and layout issues including multi-cycle race
conditions, clock domain crossing, cell and routing congestion, signal
integrity violations, and IR-drop violations
. Executed equivalence checking from RTL to tapeout netlist.
IBM, Encinitas, CA 1997 - 2000
Engineer, Digital ASIC Design
Designed three generations of Commquest's Vocoder DSP
. Designed and Implemented Finite State Machines (FSM) to control 5-
stage pipeline.
. Op-code fetch and decode, Read/Write Collisions
. Pipeline Stalls, Zero-overhead loops, Conditional Branches
EDUCATION
B.S. Computer Engineering, Illinois Institute of Technology
. Implemented RISC 5-stage pipeline processor in VHDL using Altera CPLD
PROFESSIONAL DEVELOPMENT
Harvard ManageMentor Program
Mastering UMTS (W-CDMA) Radio Networks
Verisity Specman Training Course
Synopsys Workshops for Chip Synthesis, Physical Compiler, PrimeTime, PTSI
Magma Boot Camp
Tensilica Training Workshop
DAC, DVCON, IEEE DS-NOC
Mentor SystemVerilog Assertions (SVA) Seminar
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