Engineer Electrical

Professional Summary:

Multifaceted Yield Engineer with 10+ years hands-on experience in

semiconductor manufacturing processes particularly in semiconductor

defect characterization, defect inspection optimization and Final

Test Electrical yield correlations with defect yields. Proven track

record of developing implementable solutions to complex

semiconductor yield related problems. Excellent project management,

communication, analytical and interpersonal skills.

Computer Skills:

Programming C++, C#, Visual Basic, Java, PL SQL

Languages

Assembly Languages VHDL, PLC, Motorola 68HC12 Micro Controller

Engineering MATLAB, Cadence OrCAD Pspice (Electronic Device

Software Simulator), Xilinx ISE (Logic Design and FPGA

programming), Remcom Xfdtd (Antenna Design and EM Wave

Simulator)

General Software Microsoft Office, Adobe Acrobat, Adobe Dreamweaver,

Packages Minitab, JMP

Databases RDBMS IBM DB2, Oracle MySQL

Operating Systems IBM OS/2, Linux, Unix, Windows NT/95/98/2000/XP/Vista

Semiconductors KLA-Tencor Klarity (Semiconductor Defect Management and

Software Packages Yield Analysis system), DES (Semiconductor Defect

Evaluator System), dataPOWER (Semiconductor Electrical

Yield Management System) SECS/GEM

Technical Skills:

. Theoretical understanding of 45nm and 35nm semiconductor device

physics and analytical familiarity with both frontend, backend

fabrication processes involved in embedded DRAM (Dynamic Read

Access Memory), PMOS (P-channel); NMOS (N-channel); CMOS

(Complementary Metal Oxide Semiconductor), Bipolar, BiCMOS, Qubic3

and Qubic4 fabrication technologies.

. Experienced in identifying, isolating, classifying and monitoring

semiconductor defects caused by Lithography, CMP (Chemical

Mechanical Planarization), RIE (Reactive Ion Etching), Chemical

Etching, Ion Implantation, Metal Deposition, Insulator Deposition

and Poly Deposition Processes.

. Extensive working knowledge of both dark field and bright field

metrology inspections tools and ADC (Automatic Defect

Classification).

. Familiarity with process optimization methods in high volume

manufacturing facility like SPC (Statistical Process Control), Six-

Sigma Green Belt, Total Quality Management(TQM), Key Performance

Indicators Improvement(KPI), Real Time Data Collection, Advanced

Process Control, OSHA, FMEA, Global 8-D and various quality/test

standards particularly in ISO9000/TS16949 (Automotive Products).

Professional Experience:

IBM, Hopewell Junction, New York (February 2010 - Present)

Title: PLY (Process Limiting Yield) Characterization Engineer

Responsibilities:

. Define/refine inspection strategies to maximize yield

learning, while not exceeding inspection time targets to

ensure containment within the inline inspection capacity

plan.

. Provide defect characterization reporting for new

technologies to improve yield, performance and reliability.

. Deliver yield paretos of key defect mechanisms and drive

closure on same with the technical community

. Deliver timely, accurate identification of trends (with

vintaging, tool analysis, etc) to assist in root cause

analysis. Identify and summarize key statistics and trends.

Characterize window/trade-offs between process stability and

performance Summarize results in a clear and concise format.

. Establish/Leverage Early Product Yield Learning vehicle(s) in

preparation of their transfer to manufacturing

. Support the qualification activities and technology

milestones and work with integration as well as process

module teams to provide timely feedback on split/process

experiments, tool quals, etc.

. Identify any yield modulation between splits and identify

process improvements.

Major Projects Highlights:

. Implementation of SSA(Spatial Signature Analysis):

. Successfully programmed and implemented SSA algorithms to

automate the detections of scratches and other macro

signatures on the wafer and generate immediate notification

to tool owners reducing the response time to yield

incursions.

. Evaluated all existing Final Wafer inspection recipes and

suggested improvements to minimize false detections which

were masking critical failure signatures.

. Identified, isolated and eliminated failure mechanisms

which were causing scraps during final wafer inspection.

NXP/Philips Semiconductors, East Fishkill, New York (June 2005 -

July 2009)

Title: Yield Engineer

Responsibilities:

. Acted as a lead engineer for KLA-Tencor AIT, KLA-Tencor

EV300, Rudolph NSX defect inspection tools and fully

qualified substitute engineer for KLA-Tencor KLA-2139, KLA-

Tencor Surfscan SP1 toolsets.

. Designed process experiments to understand and eliminate

yield loss mechanisms. Interacted with manufacturing,

development, and Failure Analysis Team to influence prompt

executing of appropriate corrective actions.

. Established routine inspection procedures to optimize

visibility of yield related excursions and continuously

revised frequency of short term inspection procedures to

avoid redundant inspections.

. Monitored inline defect performance using Statistical Process

Control (SPC) and develop/coordinate out of control action

plans, in compliance to Six Sigma Process Controls. Generated

work orders for unscheduled PM (Preventive Maintenance) tasks

based on tool specific defect trends.

. Analyzed inline electrical tests results against established

defect density targets to characterize the current process of

record (POR). Correlated FM (Foreign Material)

classifications codes to Electrical loss parameters at Final

Test to generate updated yield projections.

. Identified and documented major yield issues and provided

weekly updates to senior management to prioritize capital and

resource allocation.

. Acted as administrator for NXP Fishkill Defect Inspection

website, Klarity Defect Inspection Web Server and MPS

(Manufacturing Procedure Specifications) owner for AIT, EV300

& NSX inspection tools.

. Interacted directly with the outside customers to provide

information about site defect trends and address any

inspection yield related concerns/complaints using Global 8D

method.

Major Projects Highlights:

. Development of Refined Broken Wafer Cleaning/Inspection

Procedure:

. Redeveloped and streamlined NXP Fishkill broken wafer

cleaning and inspection procedures to reduce unnecessary

scrap losses which were traditionally a great source of

lost revenue.

. Worked closely with WETS process engineer to eliminate non-

value-added cleaning operation and introduce backside brush

clean before batch cleaning.

. Retooled defect classification codes for broken wafer

inspections based on process level so that their defect

kill-factor ratio correlates with the Final Test electrical

testing.

. Proposed changed to broken wafer cleaning and inspection

were accepted by site TRB (Technical Review Board)

resulting 50% reduction in broken wafer scraps evaluated

over last year with no associated losses in Final Test

electrical yield or reliability stress test results.

. Implementation of Automated Final Wafer Inspections at NXP

Fishkill using Rudolph NSX:

. Proposed and administered the introduction of Rudolph NSX

at NXP Fishkill to do 100% final wafer inspection of

automotive products. The tool was released for

manufacturing within couple of months before customer

timeline.

. Wrote detailed specifications for IT team to develop custom

tasks through SECS interface and automate the generation of

defect inspection files which are sent to the customer in

advance to sort out visually inspected defective dies.

. Established automated review procedures and classification

codes to sort out actual defects from process variations.

. Documented all tool maintenance and recipe changes logs as

per ISO audit standards.

. Klarity Defect Management Server Administration:

. Performed general Klarity server administration tasks like

user access, space allocation, data archiving, data

retrieval and data modification.

. Worked directly with the vendor over the phone to resolve

any technical server issues.

. Volunteered and installed database and server updates to

Klarity server generating a saving of $60,000.00/year

service contract costs.

. Created client scripts using open source IDE SharpDevelop

which automated the formatting of NXP Fishkill WIP data

into Klarity recognized file format. This enabled quick

sorting of inspection data history based on job runtime

history saving considerable engineering hours wasted in

data mining.

Philips Semiconductors, East Fishkill, N.Y. (Feb 2000- May 2005)

Title: KLA-Technician

Responsibilities:

. Provided engineering supervision to manufacturing operators

and assist engineering in coordinating inspection

experiments.

. Created complex inspection recipes to optimize defect

detection and prepared failure analysis reports.

. Trained and certified operators on defect detection and SEM

(Scanning Electron Microscopy) review techniques.

. Responsiblities also included workload management, tool

optimization, scrap reduction, shift communication continuity

and first calls technical resolution of issues and error

recovery.

. Certified operator for Keithley wafer probers.

IBM, Poughkeepsie, NY (March 1999 - Jan 2000)

Title: Furnace Operator

. Certified Furnace Operator

. Responsibilities included knowledge of temperature curves,

substrate formation and cycle time monitoring.

Education:

State University of New York at New Paltz, New Paltz - NY

. Master of Science in Electrical & Computer Engineering

Expected: Dec 2010 GPA: 3.53

State University of New York at New Paltz, New Paltz - NY

. Bachelors of Science in Electrical & Computer Engineering

Dec 2006 GPA: 3.42

Dutchess Community College, Poughkeepsie - NY

. Associates in Engineering Science Aug

2003 GPA: 3.89

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