Engineer Test

JEEMIL SHAH

**** ********* *** #**, *** Diego CA-92126

Ph: 619-***-****

Email:abkfnn@r.postjobfree.com

Objective: To seek a challenging position in the field of wireless

communication

Summary: 3 years of Experience in Physical layer Verification, Protocol

Testing, Algorithm Verification and Automated Test Software Development

for OFDM/CDMA/EVDO based wireless systems

Good Understanding of multiple protocols: CDMA/EVDO Rev0/A,

802.11,FLO(Broadcast)

Worked on lab and live air performance testing,analyzing and

characterization of 3GPP2

IS856A CDMA/1xEVDO protocol,MPS testing and Spirent Testing.

Carrying out automation related tasks (scripting using Perl)

Experience:

System Test Engineer at Qualcomm:

(Jan'10- Present)

Responsibility:Understand the internal architecture of the OFDM based

receiver modem to provide help to design tests to verify the performance

of each functional block within the modem and debug issues at various

stage of verification

Asic verification: Part of team responsible for carrying out hardware

verification on emulation platform pre tapeout and Asic post tapeout.

Carried out both functional as well as performance verification for end-

end system.

Feature/Algorithm Verification:Early Exit (Power Saving Mode) : Designed

the test plan for early exit feature intended for power saving mechanism.

Was involved in algorithm verification as well as FW/SW interface

verification.

Verified multiple feature implementation like Doppler rotation, Adaptive

Thresholding for newly implemented modem architecture.

Acceptance/Regression Testing: Carried out the planning and execution of

the Physical layer acceptance and performance test plans (in lab and in

field) for the products and designed the automation and post processing

tools in Perl

Field Test Engineer at Airvana Inc (Co-op): (Sep'09

-Dec'09)

Performing live air performance testing, analyzing and characterizing of

CDMA 1x EVDO products and lab trials

Measuring and characterizing certain system performance metrics like

throughput, latency, session/connection setup, DRC/DSC switching,

forward/reverse link throughput, call setup and handoff success rate

Systems Test Engineer at Qualcomm Inc (Intern)

(April'08-April'09)

Spirent Testing: Responsible for performing tests on customer supported

Spirent automation and debugging the problems related to same. Also was

involved in verification of Spirent automation test procedure as well as

Verizon Specific testing

Performed manual as well as carried out automation test on Agilent8960 as

per IS856 Minimum Parameter Specification (MPS) for 1xEVDO and debugging

the involved failures

Part of team responsible for carrying Modem as well as RF integration &

testing, analyzing the test results for each and working closely with the

systems team in resolving the issues

Carried out Perl scripting for performing automation tasks for MPS test

cases and verifying the functionality of the test

Device Selection Algorithm: Worked on Device Selection Algorithm

(Equalizers vs. Rake) for performing demodulation to achieve optimal

throughput performance for fading scenario

Awards: Recipient of QualStar for excellent performance at Qualcomm

Skill Set: Languages: C, VHDL, PERL

Protocols: CDMA2000, 1XEVDO REV0/A,802.11 a/b/g, FLO/EV(OFDM

based broadcast)

Tools: Agilent 8960, QXDM, QPST, Spectrum Analyzer, Perl

Debugger, Windcatcher, Logic Analyzer

Certificate: Cisco Certified Network Associate (CCNA)

Thesis In: Channel Selection in Multi-Channel Mac protocol

Utilizing the non-overlapping channels available in 802.11

architecture by allowing multiple user transmission such that overall

throughput gain is achieved

Education: MS Electrical and Computer Engineering

San Diego State University (GPA 3.3)

Projects: Whynet Protocol: Designed a TDMA based MAC protocol to achieve

QoS for isochronous and asynchronous packet transmission. Slot Management

was performed at AP for compatibility with 802.11 CSMA based

architecture.

UART: Various blocks of Asynchronous Transmitter and Receiver were

made and control was done using FSM. Post-map simulation was performed

using Xilinx

Courses: Computer Networks, High Speed Network Design, Digital

Communication, Digital Signal Processing, Modern Communication, VLSI

Circuit, ASIC Design

Reference: Available upon request

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