Engineer Project Manager

Arthur D. Collard

**** ***** ***** ***** . ***** Rock, TX 78665 . 512-***-**** (cell) . 512-

***-**** (home)

abk8zd@r.postjobfree.com

SUMMARY OF QUALIFICATIONS

A proven technical professional leader with extensive experience in

automotive, industrial, and consumer electronics industries. Areas of

expertise include Project, Program and Team Management, with strong

technical and product development environments. Proven leadership

abilities with an innovative approach to project planning and a team-

focused orientation to solutions. Demonstrated success in process

improvements, project planning, and commitments to meeting goals,

milestone and end deliverables, and quality standards through technical

knowledge, resourcefulness, and collaboration with excellent

interpersonal communications skills.

SELECTED ACCOMPLISHMENTS

Project/Program Management

Technical Project Manager supporting Flash new product development and

support of CAD/Methodology groups. Directly responsible over multiple

local and worldwide business unit team-based projects. Responsible for

support of all PM process and procedure documentation. Results:

Responsibility over project stakeholders cross-functional matrix groups to

assure alignment, planning, schedule, resources, execution, best

practices, and achieving project goals were met for three separate design

projects. Key contributor for creation and launch of design phase review

templates improving milestone meetings. Enhanced design milestone quality

checklists. Rolled out transfer of technology and methodologies between

new and existing design centers for consistency across WW design centers.

Organized and held successful 4 day technical F2F meeting with new capture

company.

Design Team Section Manager. Analog and mixed signal design team section.

Responsible for development of analog IP, IO Pad cell libraries, ESD and

EMI suppression supporting all 8 and 16-bit microcontroller product

families. Results: Manage resources, team alignment, scheduling, assisting

project management, performing technical mentoring, conflict and retention

management, in partnership and collaboration with other world wide (India,

Brazil) design centers and counterparts to achieve best solutions for all

analog/mixed signal blocks and IO pads. Able to gain acceptance over

sensitive situations with direct reports. Developed successful power

management portfolio. Successfully transferred Power management IP

technology to India team for reuse. Drove development of an IP test

vehicle used to verify analog and IO pad circuitry assuring first silicon

success. Worked with Brazil team to transfer specialized BOA IO pad by

training Brazil engineer locally. First time development of a standard

cell IO pad library which included implementation guidelines and detailed

supporting datasheets.

Supervisor IO pad development. Development lead for a centralized IO pad

library in 0.35uM technology used for all local and remote design centers

supporting the 8-bit microcontroller family. Results: As a key

contributor/manager over project the library development was achieved on

time meeting first four product tapeouts. Development achieve electrical

performance and ESD levels consistency across the division. Created IO pad

and ESD protection guidelines to support integration of library

components. Supported remote design teams to utilize and implement I/O pad

library cells for these products. Was able to influence peers to gain

confidence in project implementation and usage.

Methodologies and Standards

Specifications. Developed a verification tagging scheme for all electrical

specification parameters for 8/16bit microcontrollers to assure all

parameters are verified. Result: This was rolled out during the design

kickoff meeting as a quality guarantee. The integrity and responsibility

of the Espec was guaranteed at every step during the design and test

development and finalized prior to tapeout.

Reuse Standards. Team leader within the sector reuse standards development

working group responsible for IO periphery interface standard. Result:

Team representing sector business units developed and completed reuse

standard on-time, rolled out training to design teams and supported

updates. This standard is in practice today.

Design Engineering

PDK Engineer. Responsible for deployment and support of Process

Development Kit (PDK) and incoming database integrity for all 3rd party

design partners (China, Israel) for Spansion Flash based technologies.

Results: Successfully completed over 12 database tapeouts in several

different technologies including running physical design verification and

database integrity checks. Improved PDK integrity and release efficiency.

Organized and collaborated with a cross functional technology and CAD team

to develop a complete and user friendly PDK in three different

technologies.

FLASH controller Design. Responsible for the development of FLASH SOC IP

development including IO Pad Library, custom circuit design, SOC flow

development, oversee SOW of 3rd party IP design development, and

deployment. Results: Assisted with the development of IO pads and padring

for SoC Flash controller. Coordinated and setup secure VNP tunnel between

3rd party (China) and Austin design teams. Worked with integration team on

padring ESD solution, created layout integration guide for and detailed

description of padring ESD including EMIR drop and supply capacitance

calculations.

IC level EMC and signal integrity. Lead role for the Motorola 32-bit and 8

& 16-bit Microcontroller divisions to develop low noise IO drivers, low

noise power/ground strategy, design guidelines for low radiated and

conducted emissions, implementation of standards for IC level EM

measurement tests, and assist customers with EM solutions for

applications. Results: Successfully completed; a low noise IO pad driver

to meet final customer radiated noise levels, an internal IC EMC design

guideline, development and implementation of SAE J1752/3 TEM cell

measurement test standard to support automotive customer base, pioneered

with SAE EMC sub-committee early on to verify standard and create a turn

key evaluation, and worked with EU applications engineers to understand

and implement a conducted emissions DUT card and test board, initiated the

setup to the IEC 61000-4-4 (EFT) standard for testing of customer

applications.

Reliability Analysis Team lead. Leader of a cross-functional team to

uncover and correct ESD/EOS, Latch-up, and yield weaknesses across several

8, 16, and 32-bit microcontroller families and across several CMOS

technologies. Results: Enabled products to complete qualification to meet

customer shipping commitments. Accomplished through performing root cause

analysis, implementing design solutions and layout enhancements, DRC

integrity improvements, design methodology improvements, quality checks,

and test program enhancements.

IO and ESD design. Implemented several IO pad designs with clamp based ESD

networks on 0.35 and 0.25 micron technologies. Successfully designed a dual

voltage I/O driver with selectable drive strengths in 0.25uM CMOS

technology. Results: First pass successes and improved the design cycle

time for implementing new IO pad and ESD protection designs through re-

usability, design methodology improvements, and quality checks. Met

customer's low power and lower EM initiative for anti-lock breaking

allowing the final product (automobile) to pass strict EU emissions

standard.

IP design engineer. Successfully designed a custom logic block for a Ford

electronics Hosted Bus Control Chip. Duties included logic design, writing

RTL code and simulation, behavioral modeling, circuit implementation and

SPICE simulation, oversee layout and physical verification, and assist with

integration. Results: Custom block intergrated in microcontroller

successfully with first pass functional success.

PROFESSIONAL WORK EXPERIENCE

Spansion LLC (Austin, TX)

PMO Design 2008 - 2009

MTS Engineer 2006 - 2008

Contract Engineer (Volt Technical Services) 2005 - 2006

Motorola Inc (now Freescale Semiconductor) (Austin, TX)

1992 - 2002

Member Technical Staff, 8/16 and 32

bit divisions

Ford Microelectronics (Colorado Springs, CO)

1985 - 1992

Engineering Senior Member II

EDUCATION & CERTIFICATIONS

B.S., Electrical Engineering, Pratt Institute of Technology

Nine semester hours towards MSEE degree, University of Colorado at

Colorado Springs.

Semester project included switched C filter design to Silicon evaluation.

Studying for PMI certification exam.

Studying PHP programing.

RELATED CLASSES/TRAINING

"Performance Excellence Awarness Training", Motorola University

"Real Time Resource Management Training", Motorola University

"High Altitude and Colaboration and Accountability", Motorola University

"Partnership Strategies:Alliances,Acquisitions and Delivering an Inclusive

Culture", Motorola University

RELATED EXPERIENCE

. Proficiency with Adobe FrameMaker, HTML, Open Office and Microsoft

Office suites.

. Knowledge and experience with behavioral modeling, RTL coding and

Verilog XL simulator.

. Knowledge and experience with Perl, C-shell, and C/C++ programming.

. Proficiency with Unix Sun Solaris platforms, SPICE, CADENCE (incl

Analog Artist) and Mentor Graphics (ICStudio) environments. Schematic

capture and layout (Virtuoso) tools.

. Knowledge and experience with DRC and LVS checks (Calibre).

. Self-motivated, innovative, energetic, team oriented, detail- and goal-

oriented individual contributor.

. Committed to meeting goals and quality standards through

resourcefulness, risk management, and good organizational skills.

Contact this candidate